refactor: serialize CH390 runtime SPI access

Move runtime CH390 transactions behind a single ch390_runtime owner so main, lwIP glue, and EXTI no longer compete for SPI access. Keep the system stable under runtime load and capture the remaining CH390 readback failure as a credible low-level device-response issue in the handoff logs.

Core/Src/main.c

@@ -36,6 +36,7 @@
 #include "config.h"
 #include "flash_param.h"
 #include "ethernetif.h"
+#include "ch390_runtime.h"
 #include "lwip/init.h"
 #include "lwip/timeouts.h"
 #include "tcp_client.h"
@@ -145,65 +146,25 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
 
 static void BootDiag_ReportCh390(void)
 {
-    uint16_t vendor_id;
-    uint16_t product_id;
-    uint8_t revision;
-    uint8_t nsr;
-    uint8_t ncr;
-    uint8_t rcr;
-    uint8_t imr;
-    uint8_t intcr;
-    uint8_t gpr;
-    uint8_t isr;
-    uint8_t ncr_before;
-    uint8_t ncr_after;
-    uint8_t intcr_before;
-    uint8_t intcr_after;
-    int link_status;
+    ch390_diag_t diag;
 
-    vendor_id = ch390_get_vendor_id();
-    product_id = ch390_get_product_id();
-    revision = ch390_get_revision();
-    nsr = ch390_read_reg(CH390_NSR);
-    ncr = ch390_read_reg(CH390_NCR);
-    rcr = ch390_read_reg(CH390_RCR);
-    imr = ch390_read_reg(CH390_IMR);
-    intcr = ch390_read_reg(CH390_INTCR);
-    gpr = ch390_read_reg(CH390_GPR);
-    isr = ch390_read_reg(CH390_ISR);
-    link_status = ch390_get_link_status();
-
-    ncr_before = ncr;
-    ch390_write_reg(CH390_NCR, (uint8_t)(ncr_before ^ NCR_FDX));
-    ncr_after = ch390_read_reg(CH390_NCR);
-    ch390_write_reg(CH390_NCR, ncr_before);
-
-    intcr_before = intcr;
-    ch390_write_reg(CH390_INTCR, (uint8_t)(INCR_TYPE_OD | INCR_POL_L));
-    intcr_after = ch390_read_reg(CH390_INTCR);
-    ch390_write_reg(CH390_INTCR, intcr_before);
+    ch390_runtime_get_diag(&diag);
 
     SEGGER_RTT_printf(0,
                       "CH390 VID=0x%04X PID=0x%04X REV=0x%02X NSR=0x%02X LINK=%d\r\n",
-                      vendor_id,
-                      product_id,
-                      revision,
-                      nsr,
-                      link_status);
+                      diag.vendor_id,
+                      diag.product_id,
+                      diag.revision,
+                      diag.nsr,
+                      diag.link_up);
     SEGGER_RTT_printf(0,
                       "CH390 NCR=0x%02X RCR=0x%02X IMR=0x%02X INTCR=0x%02X GPR=0x%02X ISR=0x%02X\r\n",
-                      ncr,
-                      rcr,
-                      imr,
-                      intcr,
-                      gpr,
-                      isr);
-    SEGGER_RTT_printf(0,
-                      "CH390 WRCHK NCR:0x%02X->0x%02X INTCR:0x%02X->0x%02X\r\n",
-                      ncr_before,
-                      ncr_after,
-                      intcr_before,
-                      intcr_after);
+                      diag.ncr,
+                      diag.rcr,
+                      diag.imr,
+                      diag.intcr,
+                      diag.gpr,
+                      diag.isr);
 }
 
 static void App_PollUart1ConfigRx(void)
@@ -313,7 +274,9 @@ static void App_Poll(void)
         NVIC_SystemReset();
     }
 
-    HAL_IWDG_Refresh(&hiwdg);
+    if (hiwdg.Instance == IWDG) {
+        HAL_IWDG_Refresh(&hiwdg);
+    }
 }
 
 /* USER CODE END 0 */
@@ -348,7 +311,7 @@ int main(void)
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
   MX_DMA_Init();
-  MX_IWDG_Init();
+  // MX_IWDG_Init();
   MX_USART1_UART_Init();
   MX_USART2_UART_Init();
   MX_USART3_UART_Init();
@@ -356,6 +319,8 @@ int main(void)
   MX_TIM4_Init();
   /* USER CODE BEGIN 2 */
   
+  ch390_hardware_reset();
+  
   /* LED 初始化 */
   LED_Init();
   LED_StartBlink();

Core/Src/spi.c

@@ -44,7 +44,7 @@ void MX_SPI1_Init(void)
   hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;   /* CH390 requires CPOL=High (Mode 3) */
   hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;        /* CH390 requires CPHA=2Edge (Mode 3) */
   hspi1.Init.NSS = SPI_NSS_SOFT;                /* Software CS control for CH390 */
-  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; /* 72MHz/8 = 9MHz (CH390 max 10MHz) */
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64; /* 72MHz/64 = 1.125MHz for low-speed CH390 bring-up */
   hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
   hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
   hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;

Core/Src/stm32f1xx_it.c

@@ -23,6 +23,7 @@
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
 #include "ethernetif.h"
+#include "ch390_runtime.h"
 #include "SEGGER_RTT.h"
 #include "uart_trans.h"
 #include "config.h"
@@ -345,8 +346,8 @@ void EXTI0_IRQHandler(void)
     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_0);
 
     /* Defer CH390 processing to main loop */
-    ethernetif_set_irq_pending();
-  }
+        ch390_runtime_set_irq_pending();
+    }
 }
 
 /**