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refactor: remove CH390 bitbang read path and sync manuals

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2026-04-02 14:36:29 +08:00
parent 81594c6520
commit 1ef1ba9490
5 changed files with 652 additions and 89 deletions
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Drivers/CH390/CH390_Interface.c
+3 -77
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@@ -61,8 +61,6 @@ extern SPI_HandleTypeDef hspi1;
/* Timeout for SPI operations (ms) */
#define SPI_TIMEOUT 100
#define CH390_BITBANG_HALF_PERIOD_US 2u
/*----------------------------------------------------------------------------
* Low-level GPIO operations
*---------------------------------------------------------------------------*/
@@ -105,63 +103,6 @@ static inline uint8_t ch390_miso(void)
return (uint8_t)(HAL_GPIO_ReadPin(CH390_MISO_PORT, CH390_MISO_PIN) == GPIO_PIN_SET);
}
static void ch390_spi_gpio_mode(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
GPIO_InitStruct.Pin = CH390_SCK_PIN | CH390_MOSI_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(CH390_SCK_PORT, &GPIO_InitStruct);
GPIO_InitStruct.Pin = CH390_MISO_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(CH390_MISO_PORT, &GPIO_InitStruct);
ch390_cs(1u);
ch390_sck(1u);
ch390_mosi(1u);
}
static void ch390_spi_restore_pins(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
GPIO_InitStruct.Pin = CH390_SCK_PIN | CH390_MOSI_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(CH390_SCK_PORT, &GPIO_InitStruct);
GPIO_InitStruct.Pin = CH390_MISO_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(CH390_MISO_PORT, &GPIO_InitStruct);
ch390_spi_init();
}
static uint8_t ch390_bitbang_exchange_byte(uint8_t byte)
{
uint8_t bit;
uint8_t rx_data = 0u;
for (bit = 0u; bit < 8u; ++bit) {
ch390_mosi((uint8_t)((byte & 0x80u) != 0u));
ch390_delay_us(CH390_BITBANG_HALF_PERIOD_US);
ch390_sck(0u);
ch390_delay_us(CH390_BITBANG_HALF_PERIOD_US);
rx_data = (uint8_t)((rx_data << 1) | ch390_miso());
ch390_sck(1u);
byte <<= 1;
ch390_delay_us(CH390_BITBANG_HALF_PERIOD_US);
}
return rx_data;
}
/*----------------------------------------------------------------------------
* SPI Communication
*---------------------------------------------------------------------------*/
@@ -260,7 +201,7 @@ void ch390_spi_init(void)
/* - CPOL = High (idle clock is high) */
/* - CPHA = 2Edge (data captured on second edge) */
ch390_spi_apply_mode(SPI_POLARITY_HIGH, SPI_PHASE_2EDGE);
ch390_spi_apply_mode(SPI_POLARITY_LOW, SPI_PHASE_1EDGE); /* Start with Mode 0 */
}
/**
@@ -311,28 +252,13 @@ void ch390_delay_us(uint32_t time)
*/
void ch390_hardware_reset(void)
{
ch390_delay_us(3000); /* Short delay before reset */
ch390_rst(0); /* Assert reset (low) */
ch390_delay_us(1000); /* Hold reset for 1ms to satisfy datasheet minimum */
ch390_delay_us(3000); /* Hold reset for 3ms to satisfy datasheet minimum */
ch390_rst(1); /* Release reset (high) */
ch390_delay_us(50000); /* Wait 50ms for CH390 to initialize reliably */
}
uint8_t ch390_bitbang_read_reg(uint8_t reg)
{
uint8_t value;
__HAL_SPI_DISABLE(&hspi1);
ch390_spi_gpio_mode();
ch390_cs(0u);
(void)ch390_bitbang_exchange_byte((uint8_t)(reg | OPC_REG_R));
value = ch390_bitbang_exchange_byte(0x00u);
ch390_cs(1u);
ch390_spi_restore_pins();
return value;
}
/*----------------------------------------------------------------------------
* CH390 Register/Memory Access Functions (SPI Mode)
*---------------------------------------------------------------------------*/