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fix: capture current ch390 and lwip debug changes

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2026-04-18 05:29:32 +08:00
parent cd48a8af68
commit 70e78a6ef6
6 changed files with 63 additions and 295 deletions
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Drivers/CH390/CH390.c
+15 -109
View File
@@ -11,8 +11,6 @@
******************************************************************************/
#include "CH390.h"
#include "CH390_Interface.h"
#include "../../App/app_runtime.h"
#include "../../Core/Inc/debug_log.h"
void ch390_probe_rx_header(uint8_t *head)
{
@@ -34,9 +32,6 @@ void ch390_probe_rx_header(uint8_t *head)
*/
uint32_t ch390_receive_packet(uint8_t *buff, uint8_t *rx_status)
{
static uint32_t s_rxrdy_miss_log_count = 0u;
uint32_t i;
uint8_t rx_ready;
uint8_t nsr;
uint16_t rx_len = 0;
uint8_t ReceiveData[4];
@@ -45,122 +40,30 @@ uint32_t ch390_receive_packet(uint8_t *buff, uint8_t *rx_status)
{
*rx_status = 0u;
}
g_eth_last_rx_fail_stage = 0u;
g_eth_last_rx_status = 0u;
g_eth_last_rx_len = 0u;
g_eth_last_rx_head0 = 0u;
g_eth_last_rx_head1 = 0u;
g_eth_last_rx_head2 = 0u;
g_eth_last_rx_head3 = 0u;
g_eth_probe_rx_status = 0u;
g_eth_probe_rx_len = 0u;
g_eth_probe_head0 = 0u;
g_eth_probe_head1 = 0u;
g_eth_probe_head2 = 0u;
g_eth_probe_head3 = 0u;
for (i = 0u; i < 32u; ++i)
{
g_eth_probe_dump[i] = 0u;
}
g_eth_reprobe_rx_status = 0u;
g_eth_reprobe_rx_len = 0u;
g_eth_reprobe_head0 = 0u;
g_eth_reprobe_head1 = 0u;
g_eth_reprobe_head2 = 0u;
g_eth_reprobe_head3 = 0u;
nsr = ch390_read_reg(CH390_NSR);
g_eth_last_nsr = nsr;
if ((nsr & NSR_RXRDY) == 0u)
{
g_eth_last_rx_fail_stage = 2u;
return 0;
}
rx_ready = 0u;
g_eth_last_rx_ready = 0u;
g_eth_last_mrcmdx = 0u;
g_eth_last_mrcmdx1 = 0u;
g_eth_last_mrrl = 0u;
g_eth_last_mrrh = 0u;
ch390_read_mem(ReceiveData, 4);
g_eth_last_rx_head0 = ReceiveData[0];
g_eth_last_rx_head1 = ReceiveData[1];
g_eth_last_rx_head2 = ReceiveData[2];
g_eth_last_rx_head3 = ReceiveData[3];
if (rx_status != 0)
{
*rx_status = ReceiveData[1];
}
rx_len = (uint16_t)ReceiveData[2] | ((uint16_t)ReceiveData[3] << 8);
g_eth_last_rx_status = ReceiveData[1];
g_eth_last_rx_len = rx_len;
if (((ReceiveData[1] & 0x3Fu) != 0u) ||
(rx_len < 14u) ||
(rx_len > CH390_PKT_MAX))
{
g_eth_last_rx_ready = rx_ready;
g_eth_last_mrcmdx = 0u;
g_eth_last_mrcmdx1 = 0u;
g_eth_last_mrrl = 0u;
g_eth_last_mrrh = 0u;
g_eth_last_rx_fail_stage = 2u;
g_eth_probe_attempted += 1u;
g_eth_probe_head0 = ReceiveData[0];
g_eth_probe_head1 = ReceiveData[1];
g_eth_probe_head2 = ReceiveData[2];
g_eth_probe_head3 = ReceiveData[3];
g_eth_probe_rx_status = ReceiveData[1];
for (i = 0u; i < 32u; ++i)
{
g_eth_probe_dump[i] = 0u;
}
g_eth_probe_rx_len = (uint32_t)rx_len;
g_eth_rx_fallback_reject_count += 1u;
s_rxrdy_miss_log_count += 1u;
if ((s_rxrdy_miss_log_count & 0xFFu) == 1u)
{
debug_log_printf("[ETH] rxhdr-bad #%lu nsr=0x%02X rr=0x%02X mrx=0x%02X mrx1=0x%02X mrr=0x%02X%02X h=%02X %02X %02X %02X\r\n",
(unsigned long)s_rxrdy_miss_log_count,
(unsigned int)nsr,
(unsigned int)rx_ready,
(unsigned int)g_eth_last_mrcmdx,
(unsigned int)g_eth_last_mrcmdx1,
(unsigned int)g_eth_last_mrrh,
(unsigned int)g_eth_last_mrrl,
(unsigned int)ReceiveData[0],
(unsigned int)ReceiveData[1],
(unsigned int)ReceiveData[2],
(unsigned int)ReceiveData[3]);
}
return 0;
}
g_eth_rx_gate_ok_count += 1u;
g_eth_rx_fallback_ok_count += 1u;
if(rx_len <= CH390_PKT_MAX)
{
ch390_read_mem(buff, rx_len);
}
else
{
g_eth_last_rx_fail_stage = 3u;
}
if ((rx_len > CH390_PKT_MAX))
{
g_eth_last_rx_fail_stage = 4u;
return 0;
}
g_eth_last_rx_fail_stage = 5u;
ch390_read_mem(buff, rx_len);
return rx_len;
}
@@ -170,24 +73,27 @@ uint32_t ch390_receive_packet(uint8_t *buff, uint8_t *rx_status)
* @param buff - Data to be sent
* @param length - Less than 3k bytes.
*/
void ch390_send_packet(uint8_t *buff, uint16_t length)
int ch390_send_packet(uint8_t *buff, uint16_t length)
{
uint32_t spin_count = 0u;
// Write data to SRAM
ch390_write_mem(buff, length);
// Wait until last transmit complete
while(ch390_read_reg(CH390_TCR) & TCR_TXREQ);
while ((ch390_read_reg(CH390_TCR) & TCR_TXREQ) != 0u)
{
++spin_count;
if (spin_count >= 4096u)
{
return -1;
}
}
// Set current packet length
ch390_write_reg(CH390_TXPLL, length & 0xff);
ch390_write_reg(CH390_TXPLH, (length >> 8) & 0xff);
// Issue transmit request
ch390_send_request();
g_eth_last_tcr_after = (uint32_t)ch390_read_reg(CH390_TCR);
g_eth_last_nsr_after = (uint32_t)ch390_read_reg(CH390_NSR);
g_eth_last_tsra = (uint32_t)ch390_read_reg(CH390_TSRA);
g_eth_last_tsrb = (uint32_t)ch390_read_reg(CH390_TSRB);
g_eth_last_txpll_rb = (uint32_t)ch390_read_reg(CH390_TXPLL);
g_eth_last_txplh_rb = (uint32_t)ch390_read_reg(CH390_TXPLH);
return 0;
}
/**
@@ -760,7 +666,7 @@ uint32_t ch390_runtime_receive_packet(uint8_t *buff, uint8_t *rx_status)
return ch390_receive_packet(buff, rx_status);
}
void ch390_runtime_send_packet(uint8_t *buff, uint16_t length)
int ch390_runtime_send_packet(uint8_t *buff, uint16_t length)
{
ch390_send_packet(buff, length);
return ch390_send_packet(buff, length);
}
Drivers/CH390/CH390.h
+2 -2
View File
@@ -392,7 +392,7 @@ uint32_t ch390_receive_packet(uint8_t *buff, uint8_t *rx_status);
* @param buff - Data to be sent
* @param length - Less than 3k bytes.
*/
void ch390_send_packet(uint8_t *buff, uint16_t length);
int ch390_send_packet(uint8_t *buff, uint16_t length);
/**
* @name ch390_send_request
@@ -672,6 +672,6 @@ uint32_t ch390_runtime_receive_packet(uint8_t *buff, uint8_t *rx_status);
* @param buff - Data to be sent
* @param length - Less than 3k bytes.
*/
void ch390_runtime_send_packet(uint8_t *buff, uint16_t length);
int ch390_runtime_send_packet(uint8_t *buff, uint16_t length);
#endif /* __CH390_H */