refactor: 完成R8裸机lwIP移植并更新文档
This commit is contained in:
+253
-450
@@ -1,528 +1,331 @@
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/**
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* @file uart_trans.c
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* @brief UART transparent transmission module implementation
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*
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* Uses DMA + IDLE interrupt for efficient variable-length data reception.
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* Integrates with TCP modules via FreeRTOS StreamBuffers.
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* @brief Bare-metal UART DMA/IDLE transport layer.
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*/
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#include "uart_trans.h"
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#include "usart.h"
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#include "FreeRTOS.h"
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#include "task.h"
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#include "stream_buffer.h"
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#include "usart.h"
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#include <string.h>
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/*---------------------------------------------------------------------------
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* Private Definitions
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*---------------------------------------------------------------------------*/
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/* Channel context structure */
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typedef struct {
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UART_HandleTypeDef *huart; /* HAL UART handle */
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DMA_HandleTypeDef *hdma_rx; /* DMA RX handle */
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uint8_t rx_dma_buffer[UART_RX_DMA_BUFFER_SIZE]; /* DMA RX buffer */
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uint8_t tx_dma_buffer[UART_TX_DMA_BUFFER_SIZE]; /* DMA TX buffer */
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volatile uint16_t rx_read_index; /* Last read position */
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volatile bool tx_busy; /* TX in progress flag */
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StreamBufferHandle_t rx_stream; /* From TCP (for UART TX) */
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StreamBufferHandle_t tx_stream; /* To TCP (from UART RX) */
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uart_config_t config; /* UART configuration */
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uart_stats_t stats; /* Statistics */
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UART_HandleTypeDef *huart;
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uint8_t rx_dma_buffer[UART_RX_DMA_BUFFER_SIZE];
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uint8_t tx_dma_buffer[UART_TX_DMA_BUFFER_SIZE];
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uint8_t rx_ring[UART_RX_RING_BUFFER_SIZE];
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uint8_t tx_ring[UART_TX_RING_BUFFER_SIZE];
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volatile uint16_t rx_dma_read_index;
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volatile uint16_t rx_head;
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volatile uint16_t rx_tail;
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volatile uint16_t tx_head;
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volatile uint16_t tx_tail;
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volatile uint16_t tx_dma_len;
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volatile bool tx_busy;
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uart_config_t config;
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uart_stats_t stats;
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bool initialized;
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bool running;
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} uart_channel_ctx_t;
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/*---------------------------------------------------------------------------
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* Private Variables
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*---------------------------------------------------------------------------*/
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static uart_channel_ctx_t g_channels[UART_CHANNEL_MAX];
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/*---------------------------------------------------------------------------
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* Private Functions
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*---------------------------------------------------------------------------*/
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static uint16_t ring_used(uint16_t head, uint16_t tail, uint16_t size)
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{
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return (head >= tail) ? (head - tail) : (size - tail + head);
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}
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static uint16_t ring_free(uint16_t head, uint16_t tail, uint16_t size)
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{
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return (uint16_t)(size - ring_used(head, tail, size) - 1u);
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}
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static void apply_default_config(uart_channel_ctx_t *ctx)
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{
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ctx->config.baudrate = UART_DEFAULT_BAUDRATE;
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ctx->config.data_bits = UART_DEFAULT_DATA_BITS;
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ctx->config.stop_bits = UART_DEFAULT_STOP_BITS;
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ctx->config.parity = UART_DEFAULT_PARITY;
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}
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/**
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* @brief Apply UART configuration
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*/
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static int apply_uart_config(uart_channel_t channel)
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{
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uart_channel_ctx_t *ctx = &g_channels[channel];
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UART_HandleTypeDef *huart = ctx->huart;
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if (huart == NULL)
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{
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if (huart == NULL) {
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return -1;
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}
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/* Stop UART if running */
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if (ctx->running)
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{
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if (ctx->running) {
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HAL_UART_DMAStop(huart);
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ctx->running = false;
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}
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/* Update UART parameters */
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huart->Init.BaudRate = ctx->config.baudrate;
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/* Data bits */
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if (ctx->config.data_bits == 9)
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{
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huart->Init.WordLength = UART_WORDLENGTH_9B;
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huart->Init.WordLength = (ctx->config.data_bits == 9u) ? UART_WORDLENGTH_9B : UART_WORDLENGTH_8B;
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huart->Init.StopBits = (ctx->config.stop_bits == 2u) ? UART_STOPBITS_2 : UART_STOPBITS_1;
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switch (ctx->config.parity) {
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case 1:
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huart->Init.Parity = UART_PARITY_ODD;
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break;
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case 2:
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huart->Init.Parity = UART_PARITY_EVEN;
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break;
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default:
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huart->Init.Parity = UART_PARITY_NONE;
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break;
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}
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else
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{
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huart->Init.WordLength = UART_WORDLENGTH_8B;
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}
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/* Stop bits */
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if (ctx->config.stop_bits == 2)
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{
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huart->Init.StopBits = UART_STOPBITS_2;
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}
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else
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{
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huart->Init.StopBits = UART_STOPBITS_1;
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}
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/* Parity */
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switch (ctx->config.parity)
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{
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case 1:
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huart->Init.Parity = UART_PARITY_ODD;
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break;
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case 2:
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huart->Init.Parity = UART_PARITY_EVEN;
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break;
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default:
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huart->Init.Parity = UART_PARITY_NONE;
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return (HAL_UART_Init(huart) == HAL_OK) ? 0 : -1;
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}
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static void process_rx_snapshot(uart_channel_t channel, uint16_t dma_write_index)
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{
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uart_channel_ctx_t *ctx = &g_channels[channel];
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while (ctx->rx_dma_read_index != dma_write_index) {
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uint16_t next_head;
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next_head = (uint16_t)((ctx->rx_head + 1u) % UART_RX_RING_BUFFER_SIZE);
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if (next_head == ctx->rx_tail) {
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ctx->stats.errors++;
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break;
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}
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ctx->rx_ring[ctx->rx_head] = ctx->rx_dma_buffer[ctx->rx_dma_read_index];
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ctx->rx_head = next_head;
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ctx->rx_dma_read_index = (uint16_t)((ctx->rx_dma_read_index + 1u) % UART_RX_DMA_BUFFER_SIZE);
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ctx->stats.rx_bytes++;
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}
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/* Reinitialize UART */
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if (HAL_UART_Init(huart) != HAL_OK)
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{
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return -1;
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}
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static void kick_tx(uart_channel_t channel)
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{
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uart_channel_ctx_t *ctx = &g_channels[channel];
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uint16_t available;
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uint16_t chunk;
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if (!ctx->running || ctx->tx_busy) {
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return;
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}
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available = ring_used(ctx->tx_head, ctx->tx_tail, UART_TX_RING_BUFFER_SIZE);
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if (available == 0u) {
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return;
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}
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chunk = available;
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if (chunk > UART_TX_DMA_BUFFER_SIZE) {
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chunk = UART_TX_DMA_BUFFER_SIZE;
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}
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for (uint16_t i = 0; i < chunk; ++i) {
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ctx->tx_dma_buffer[i] = ctx->tx_ring[ctx->tx_tail];
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ctx->tx_tail = (uint16_t)((ctx->tx_tail + 1u) % UART_TX_RING_BUFFER_SIZE);
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}
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ctx->tx_dma_len = chunk;
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ctx->tx_busy = true;
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ctx->stats.tx_packets++;
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if (HAL_UART_Transmit_DMA(ctx->huart, ctx->tx_dma_buffer, chunk) != HAL_OK) {
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ctx->tx_busy = false;
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ctx->stats.errors++;
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}
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}
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int uart_trans_init(void)
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{
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memset(g_channels, 0, sizeof(g_channels));
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g_channels[UART_CHANNEL_SERVER].huart = &huart2;
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g_channels[UART_CHANNEL_CLIENT].huart = &huart3;
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apply_default_config(&g_channels[UART_CHANNEL_SERVER]);
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apply_default_config(&g_channels[UART_CHANNEL_CLIENT]);
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g_channels[UART_CHANNEL_SERVER].initialized = true;
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g_channels[UART_CHANNEL_CLIENT].initialized = true;
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return 0;
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}
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static void process_rx_data_from_isr(uart_channel_t channel, uint16_t end_index)
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int uart_trans_config(uart_channel_t channel, const uart_config_t *config)
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{
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uart_channel_ctx_t *ctx = &g_channels[channel];
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uint16_t start = ctx->rx_read_index;
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uint16_t end = end_index;
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uint16_t len;
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BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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if (start >= UART_RX_DMA_BUFFER_SIZE)
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{
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start = 0;
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if (channel >= UART_CHANNEL_MAX || config == NULL) {
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return -1;
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}
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if (end > UART_RX_DMA_BUFFER_SIZE)
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{
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end = UART_RX_DMA_BUFFER_SIZE;
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g_channels[channel].config = *config;
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return apply_uart_config(channel);
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}
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int uart_trans_start(uart_channel_t channel)
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{
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uart_channel_ctx_t *ctx;
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if (channel >= UART_CHANNEL_MAX) {
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return -1;
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}
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if (end >= start)
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{
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len = end - start;
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if (len > 0 && ctx->tx_stream != NULL)
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{
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xStreamBufferSendFromISR(ctx->tx_stream,
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&ctx->rx_dma_buffer[start],
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len,
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&xHigherPriorityTaskWoken);
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ctx->stats.rx_bytes += len;
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ctx->stats.rx_packets++;
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}
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ctx = &g_channels[channel];
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if (!ctx->initialized || ctx->huart == NULL) {
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return -1;
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}
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else
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{
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len = UART_RX_DMA_BUFFER_SIZE - start;
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if (len > 0 && ctx->tx_stream != NULL)
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{
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xStreamBufferSendFromISR(ctx->tx_stream,
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&ctx->rx_dma_buffer[start],
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len,
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&xHigherPriorityTaskWoken);
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ctx->stats.rx_bytes += len;
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}
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if (end > 0 && ctx->tx_stream != NULL)
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{
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xStreamBufferSendFromISR(ctx->tx_stream,
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ctx->rx_dma_buffer,
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end,
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&xHigherPriorityTaskWoken);
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ctx->stats.rx_bytes += end;
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}
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ctx->rx_dma_read_index = 0u;
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ctx->rx_head = 0u;
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ctx->rx_tail = 0u;
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ctx->tx_head = 0u;
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ctx->tx_tail = 0u;
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ctx->tx_dma_len = 0u;
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ctx->tx_busy = false;
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__HAL_UART_ENABLE_IT(ctx->huart, UART_IT_IDLE);
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if (HAL_UART_Receive_DMA(ctx->huart, ctx->rx_dma_buffer, UART_RX_DMA_BUFFER_SIZE) != HAL_OK) {
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return -1;
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}
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ctx->running = true;
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return 0;
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}
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int uart_trans_stop(uart_channel_t channel)
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{
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if (channel >= UART_CHANNEL_MAX) {
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return -1;
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}
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HAL_UART_DMAStop(g_channels[channel].huart);
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g_channels[channel].running = false;
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g_channels[channel].tx_busy = false;
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return 0;
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}
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void uart_trans_get_stats(uart_channel_t channel, uart_stats_t *stats)
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{
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if (channel >= UART_CHANNEL_MAX || stats == NULL) {
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return;
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}
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*stats = g_channels[channel].stats;
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}
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void uart_trans_reset_stats(uart_channel_t channel)
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{
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if (channel >= UART_CHANNEL_MAX) {
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return;
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}
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memset(&g_channels[channel].stats, 0, sizeof(g_channels[channel].stats));
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}
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uint16_t uart_trans_rx_available(uart_channel_t channel)
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{
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if (channel >= UART_CHANNEL_MAX) {
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return 0u;
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}
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return ring_used(g_channels[channel].rx_head, g_channels[channel].rx_tail, UART_RX_RING_BUFFER_SIZE);
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}
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uint16_t uart_trans_read(uart_channel_t channel, uint8_t *data, uint16_t max_len)
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{
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uart_channel_ctx_t *ctx;
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uint16_t copied = 0u;
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if (channel >= UART_CHANNEL_MAX || data == NULL || max_len == 0u) {
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return 0u;
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}
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ctx = &g_channels[channel];
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while (copied < max_len && ctx->rx_tail != ctx->rx_head) {
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data[copied++] = ctx->rx_ring[ctx->rx_tail];
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ctx->rx_tail = (uint16_t)((ctx->rx_tail + 1u) % UART_RX_RING_BUFFER_SIZE);
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}
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if (copied > 0u) {
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ctx->stats.rx_packets++;
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}
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ctx->rx_read_index = (end == UART_RX_DMA_BUFFER_SIZE) ? 0 : end;
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portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
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return copied;
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}
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/*---------------------------------------------------------------------------
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* Public Functions
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*---------------------------------------------------------------------------*/
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/**
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* @brief Initialize UART transparent transmission module
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*/
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int uart_trans_init(void)
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uint16_t uart_trans_write(uart_channel_t channel, const uint8_t *data, uint16_t len)
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{
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/* Initialize Server channel (UART2) */
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memset(&g_channels[UART_CHANNEL_SERVER], 0, sizeof(uart_channel_ctx_t));
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g_channels[UART_CHANNEL_SERVER].huart = &huart2;
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g_channels[UART_CHANNEL_SERVER].config.baudrate = UART_DEFAULT_BAUDRATE;
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g_channels[UART_CHANNEL_SERVER].config.data_bits = UART_DEFAULT_DATA_BITS;
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g_channels[UART_CHANNEL_SERVER].config.stop_bits = UART_DEFAULT_STOP_BITS;
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g_channels[UART_CHANNEL_SERVER].config.parity = UART_DEFAULT_PARITY;
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g_channels[UART_CHANNEL_SERVER].initialized = true;
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/* Initialize Client channel (UART3) */
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memset(&g_channels[UART_CHANNEL_CLIENT], 0, sizeof(uart_channel_ctx_t));
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g_channels[UART_CHANNEL_CLIENT].huart = &huart3;
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g_channels[UART_CHANNEL_CLIENT].config.baudrate = UART_DEFAULT_BAUDRATE;
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g_channels[UART_CHANNEL_CLIENT].config.data_bits = UART_DEFAULT_DATA_BITS;
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g_channels[UART_CHANNEL_CLIENT].config.stop_bits = UART_DEFAULT_STOP_BITS;
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g_channels[UART_CHANNEL_CLIENT].config.parity = UART_DEFAULT_PARITY;
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g_channels[UART_CHANNEL_CLIENT].initialized = true;
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return 0;
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uart_channel_ctx_t *ctx;
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uint16_t written = 0u;
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if (channel >= UART_CHANNEL_MAX || data == NULL || len == 0u) {
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return 0u;
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}
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ctx = &g_channels[channel];
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while (written < len && ring_free(ctx->tx_head, ctx->tx_tail, UART_TX_RING_BUFFER_SIZE) > 0u) {
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ctx->tx_ring[ctx->tx_head] = data[written++];
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ctx->tx_head = (uint16_t)((ctx->tx_head + 1u) % UART_TX_RING_BUFFER_SIZE);
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}
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if (written < len) {
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ctx->stats.errors++;
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}
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kick_tx(channel);
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return written;
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}
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/**
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* @brief Configure UART channel parameters
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*/
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int uart_trans_config(uart_channel_t channel, const uart_config_t *config)
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void uart_trans_poll(void)
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{
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if (channel >= UART_CHANNEL_MAX || config == NULL)
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{
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return -1;
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}
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uart_channel_ctx_t *ctx = &g_channels[channel];
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memcpy(&ctx->config, config, sizeof(uart_config_t));
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/* Apply configuration if already initialized */
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if (ctx->initialized)
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{
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return apply_uart_config(channel);
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}
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return 0;
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kick_tx(UART_CHANNEL_SERVER);
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kick_tx(UART_CHANNEL_CLIENT);
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}
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/**
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* @brief Start UART reception
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*/
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int uart_trans_start(uart_channel_t channel)
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{
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if (channel >= UART_CHANNEL_MAX)
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{
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return -1;
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}
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uart_channel_ctx_t *ctx = &g_channels[channel];
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if (!ctx->initialized || ctx->huart == NULL)
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{
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return -1;
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}
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/* Reset read index */
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ctx->rx_read_index = 0;
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ctx->tx_busy = false;
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/* Enable IDLE interrupt */
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__HAL_UART_ENABLE_IT(ctx->huart, UART_IT_IDLE);
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/* Start DMA reception (circular mode) */
|
||||
HAL_UART_Receive_DMA(ctx->huart, ctx->rx_dma_buffer, UART_RX_DMA_BUFFER_SIZE);
|
||||
|
||||
ctx->running = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop UART reception
|
||||
*/
|
||||
int uart_trans_stop(uart_channel_t channel)
|
||||
{
|
||||
if (channel >= UART_CHANNEL_MAX)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
uart_channel_ctx_t *ctx = &g_channels[channel];
|
||||
|
||||
if (ctx->huart == NULL)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Disable IDLE interrupt */
|
||||
__HAL_UART_DISABLE_IT(ctx->huart, UART_IT_IDLE);
|
||||
|
||||
/* Stop DMA */
|
||||
HAL_UART_DMAStop(ctx->huart);
|
||||
|
||||
ctx->running = false;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set StreamBuffer handles
|
||||
*/
|
||||
void uart_trans_set_streams(uart_channel_t channel,
|
||||
void *rx_stream,
|
||||
void *tx_stream)
|
||||
{
|
||||
if (channel >= UART_CHANNEL_MAX)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
g_channels[channel].rx_stream = (StreamBufferHandle_t)rx_stream;
|
||||
g_channels[channel].tx_stream = (StreamBufferHandle_t)tx_stream;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get UART statistics
|
||||
*/
|
||||
void uart_trans_get_stats(uart_channel_t channel, uart_stats_t *stats)
|
||||
{
|
||||
if (channel >= UART_CHANNEL_MAX || stats == NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
memcpy(stats, &g_channels[channel].stats, sizeof(uart_stats_t));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset UART statistics
|
||||
*/
|
||||
void uart_trans_reset_stats(uart_channel_t channel)
|
||||
{
|
||||
if (channel >= UART_CHANNEL_MAX)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
memset(&g_channels[channel].stats, 0, sizeof(uart_stats_t));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UART IDLE interrupt handler
|
||||
*/
|
||||
void uart_trans_idle_handler(uart_channel_t channel)
|
||||
{
|
||||
if (channel >= UART_CHANNEL_MAX)
|
||||
{
|
||||
UART_HandleTypeDef *huart;
|
||||
uint16_t dma_write_index;
|
||||
|
||||
if (channel >= UART_CHANNEL_MAX) {
|
||||
return;
|
||||
}
|
||||
|
||||
uart_channel_ctx_t *ctx = &g_channels[channel];
|
||||
|
||||
if (!ctx->running || ctx->huart == NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Get current DMA position */
|
||||
uint16_t dma_counter = __HAL_DMA_GET_COUNTER(ctx->huart->hdmarx);
|
||||
uint16_t current_pos = UART_RX_DMA_BUFFER_SIZE - dma_counter;
|
||||
|
||||
/* Process received data */
|
||||
if (current_pos != ctx->rx_read_index)
|
||||
{
|
||||
process_rx_data_from_isr(channel, current_pos);
|
||||
|
||||
huart = g_channels[channel].huart;
|
||||
dma_write_index = (uint16_t)(UART_RX_DMA_BUFFER_SIZE - __HAL_DMA_GET_COUNTER(huart->hdmarx));
|
||||
if (dma_write_index >= UART_RX_DMA_BUFFER_SIZE) {
|
||||
dma_write_index = 0u;
|
||||
}
|
||||
|
||||
process_rx_snapshot(channel, dma_write_index);
|
||||
}
|
||||
|
||||
void uart_trans_rx_half_cplt_handler(uart_channel_t channel)
|
||||
{
|
||||
if (channel >= UART_CHANNEL_MAX)
|
||||
{
|
||||
if (channel >= UART_CHANNEL_MAX) {
|
||||
return;
|
||||
}
|
||||
|
||||
uart_channel_ctx_t *ctx = &g_channels[channel];
|
||||
if (!ctx->running || ctx->huart == NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
uint16_t dma_counter = __HAL_DMA_GET_COUNTER(ctx->huart->hdmarx);
|
||||
uint16_t current_pos = UART_RX_DMA_BUFFER_SIZE - dma_counter;
|
||||
|
||||
if (current_pos != ctx->rx_read_index)
|
||||
{
|
||||
process_rx_data_from_isr(channel, current_pos);
|
||||
}
|
||||
process_rx_snapshot(channel, UART_RX_DMA_BUFFER_SIZE / 2u);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UART DMA RX complete callback (buffer half/full)
|
||||
*/
|
||||
void uart_trans_rx_cplt_handler(uart_channel_t channel)
|
||||
{
|
||||
/* In circular mode, this is called when buffer is full */
|
||||
/* The IDLE handler already processes data continuously */
|
||||
/* This is a safety handler for high-speed continuous data */
|
||||
|
||||
if (channel >= UART_CHANNEL_MAX)
|
||||
{
|
||||
if (channel >= UART_CHANNEL_MAX) {
|
||||
return;
|
||||
}
|
||||
|
||||
uart_channel_ctx_t *ctx = &g_channels[channel];
|
||||
|
||||
if (!ctx->running)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
uint16_t dma_counter = __HAL_DMA_GET_COUNTER(ctx->huart->hdmarx);
|
||||
uint16_t current_pos = UART_RX_DMA_BUFFER_SIZE - dma_counter;
|
||||
|
||||
if (current_pos != ctx->rx_read_index)
|
||||
{
|
||||
process_rx_data_from_isr(channel, current_pos);
|
||||
}
|
||||
process_rx_snapshot(channel, 0u);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UART DMA TX complete callback
|
||||
*/
|
||||
void uart_trans_tx_cplt_handler(uart_channel_t channel)
|
||||
{
|
||||
if (channel >= UART_CHANNEL_MAX)
|
||||
{
|
||||
if (channel >= UART_CHANNEL_MAX) {
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
g_channels[channel].tx_busy = false;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Server transparent transmission task (UART2 <-> TCP Server)
|
||||
*/
|
||||
void uart_server_trans_task(void *argument)
|
||||
{
|
||||
uart_channel_ctx_t *ctx = &g_channels[UART_CHANNEL_SERVER];
|
||||
uint8_t tx_buffer[128];
|
||||
size_t len;
|
||||
|
||||
(void)argument;
|
||||
|
||||
/* Wait for streams to be set */
|
||||
while (ctx->rx_stream == NULL || ctx->tx_stream == NULL)
|
||||
{
|
||||
vTaskDelay(pdMS_TO_TICKS(100));
|
||||
}
|
||||
|
||||
/* Start UART reception */
|
||||
uart_trans_start(UART_CHANNEL_SERVER);
|
||||
|
||||
while (1)
|
||||
{
|
||||
/* Check for data from TCP to send to UART */
|
||||
if (!ctx->tx_busy && ctx->rx_stream != NULL)
|
||||
{
|
||||
len = xStreamBufferReceive(ctx->rx_stream, tx_buffer,
|
||||
sizeof(tx_buffer), pdMS_TO_TICKS(10));
|
||||
if (len > 0)
|
||||
{
|
||||
/* Copy to DMA buffer and send */
|
||||
memcpy(ctx->tx_dma_buffer, tx_buffer, len);
|
||||
ctx->tx_busy = true;
|
||||
|
||||
if (HAL_UART_Transmit_DMA(ctx->huart, ctx->tx_dma_buffer, len) != HAL_OK)
|
||||
{
|
||||
ctx->tx_busy = false;
|
||||
ctx->stats.errors++;
|
||||
}
|
||||
else
|
||||
{
|
||||
ctx->stats.tx_bytes += len;
|
||||
ctx->stats.tx_packets++;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* TX busy or no stream, wait a bit */
|
||||
vTaskDelay(pdMS_TO_TICKS(1));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Client transparent transmission task (UART3 <-> TCP Client)
|
||||
*/
|
||||
void uart_client_trans_task(void *argument)
|
||||
{
|
||||
uart_channel_ctx_t *ctx = &g_channels[UART_CHANNEL_CLIENT];
|
||||
uint8_t tx_buffer[128];
|
||||
size_t len;
|
||||
|
||||
(void)argument;
|
||||
|
||||
/* Wait for streams to be set */
|
||||
while (ctx->rx_stream == NULL || ctx->tx_stream == NULL)
|
||||
{
|
||||
vTaskDelay(pdMS_TO_TICKS(100));
|
||||
}
|
||||
|
||||
/* Start UART reception */
|
||||
uart_trans_start(UART_CHANNEL_CLIENT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
/* Check for data from TCP to send to UART */
|
||||
if (!ctx->tx_busy && ctx->rx_stream != NULL)
|
||||
{
|
||||
len = xStreamBufferReceive(ctx->rx_stream, tx_buffer,
|
||||
sizeof(tx_buffer), pdMS_TO_TICKS(10));
|
||||
if (len > 0)
|
||||
{
|
||||
/* Copy to DMA buffer and send */
|
||||
memcpy(ctx->tx_dma_buffer, tx_buffer, len);
|
||||
ctx->tx_busy = true;
|
||||
|
||||
if (HAL_UART_Transmit_DMA(ctx->huart, ctx->tx_dma_buffer, len) != HAL_OK)
|
||||
{
|
||||
ctx->tx_busy = false;
|
||||
ctx->stats.errors++;
|
||||
}
|
||||
else
|
||||
{
|
||||
ctx->stats.tx_bytes += len;
|
||||
ctx->stats.tx_packets++;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* TX busy or no stream, wait a bit */
|
||||
vTaskDelay(pdMS_TO_TICKS(1));
|
||||
}
|
||||
}
|
||||
g_channels[channel].stats.tx_bytes += g_channels[channel].tx_dma_len;
|
||||
g_channels[channel].tx_dma_len = 0u;
|
||||
kick_tx(channel);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user