gaoro-xiao/TCP2UART
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases 3 Wiki Activity

gitignore: 添加Keil MDK用户配置和构建输出；提交ioc更新

Browse Source
This commit is contained in:
😍
2026-03-29 17:19:15 +08:00
parent 06c3c9b46f
commit ac32ce8030
13 changed files with 135474 additions and 475 deletions
Download Patch File Download Diff File Expand all files Collapse all files
TCP2UART.ioc
+42 -41
View File
@@ -4,29 +4,29 @@ CAD.pinconfig=
CAD.provider=
Dma.Request0=USART2_RX
Dma.Request1=USART2_TX
Dma.Request2=USART3_RX
Dma.Request3=USART3_TX
Dma.Request4=USART1_RX
Dma.Request5=USART1_TX
Dma.Request2=USART1_RX
Dma.Request3=USART1_TX
Dma.Request4=USART3_RX
Dma.Request5=USART3_TX
Dma.RequestsNb=6
Dma.USART1_RX.4.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART1_RX.4.Instance=DMA1_Channel5
Dma.USART1_RX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_RX.4.MemInc=DMA_MINC_ENABLE
Dma.USART1_RX.4.Mode=DMA_NORMAL
Dma.USART1_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_RX.4.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_RX.4.Priority=DMA_PRIORITY_LOW
Dma.USART1_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.USART1_TX.5.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART1_TX.5.Instance=DMA1_Channel4
Dma.USART1_TX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_TX.5.MemInc=DMA_MINC_ENABLE
Dma.USART1_TX.5.Mode=DMA_NORMAL
Dma.USART1_TX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_TX.5.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_TX.5.Priority=DMA_PRIORITY_LOW
Dma.USART1_TX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.USART1_RX.2.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART1_RX.2.Instance=DMA1_Channel5
Dma.USART1_RX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_RX.2.MemInc=DMA_MINC_ENABLE
Dma.USART1_RX.2.Mode=DMA_NORMAL
Dma.USART1_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_RX.2.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_RX.2.Priority=DMA_PRIORITY_LOW
Dma.USART1_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.USART1_TX.3.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART1_TX.3.Instance=DMA1_Channel4
Dma.USART1_TX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_TX.3.MemInc=DMA_MINC_ENABLE
Dma.USART1_TX.3.Mode=DMA_NORMAL
Dma.USART1_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_TX.3.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_TX.3.Priority=DMA_PRIORITY_LOW
Dma.USART1_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.USART2_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART2_RX.0.Instance=DMA1_Channel6
Dma.USART2_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
@@ -45,24 +45,24 @@ Dma.USART2_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART2_TX.1.PeriphInc=DMA_PINC_DISABLE
Dma.USART2_TX.1.Priority=DMA_PRIORITY_LOW
Dma.USART2_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.USART3_RX.2.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART3_RX.2.Instance=DMA1_Channel3
Dma.USART3_RX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_RX.2.MemInc=DMA_MINC_ENABLE
Dma.USART3_RX.2.Mode=DMA_NORMAL
Dma.USART3_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_RX.2.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_RX.2.Priority=DMA_PRIORITY_LOW
Dma.USART3_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.USART3_TX.3.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART3_TX.3.Instance=DMA1_Channel2
Dma.USART3_TX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_TX.3.MemInc=DMA_MINC_ENABLE
Dma.USART3_TX.3.Mode=DMA_NORMAL
Dma.USART3_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_TX.3.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_TX.3.Priority=DMA_PRIORITY_LOW
Dma.USART3_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.USART3_RX.4.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART3_RX.4.Instance=DMA1_Channel3
Dma.USART3_RX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_RX.4.MemInc=DMA_MINC_ENABLE
Dma.USART3_RX.4.Mode=DMA_NORMAL
Dma.USART3_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_RX.4.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_RX.4.Priority=DMA_PRIORITY_LOW
Dma.USART3_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
Dma.USART3_TX.5.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART3_TX.5.Instance=DMA1_Channel2
Dma.USART3_TX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_TX.5.MemInc=DMA_MINC_ENABLE
Dma.USART3_TX.5.Mode=DMA_NORMAL
Dma.USART3_TX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_TX.5.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_TX.5.Priority=DMA_PRIORITY_LOW
Dma.USART3_TX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
FREERTOS.IPParameters=Tasks01
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL
File.Version=6
@@ -131,7 +131,7 @@ NVIC.SavedSystickIrqHandlerGenerated=true
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true\:false\:true\:false
NVIC.USART1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.USART2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.USART3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.USART3_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
PA10.Mode=Asynchronous
PA10.Signal=USART1_RX
@@ -255,3 +255,4 @@ VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom
rtos.0.ip=FREERTOS