feat(ch390): optimize SPI transfer, MAC fallback, and build settings for V1.0.0

- increase UART DMA/ring buffer sizes for mux traffic
- switch SPI1 to Mode0 with prescaler /2 and align CubeMX settings
- refactor CH390 memory read/write path with chunked SPI read and HAL bulk write
- fallback to hardware MAC when configured MAC is invalid (all-zero)
- add mux frame RTT logs and remove redundant UART1 polling
- update Keil post-build viewer integration and include build viewer artifacts
- update AT manual with all-zero MAC behavior
This commit is contained in:
2026-04-05 03:47:54 +08:00
parent c5b2bdd2d2
commit efb88ea367
11 changed files with 143 additions and 41 deletions
+4 -4
View File
@@ -26,10 +26,10 @@ typedef struct {
uint8_t payload[256];
} uart_mux_frame_t;
#define UART_RX_DMA_BUFFER_SIZE 128u
#define UART_TX_DMA_BUFFER_SIZE 128u
#define UART_RX_RING_BUFFER_SIZE 256u
#define UART_TX_RING_BUFFER_SIZE 256u
#define UART_RX_DMA_BUFFER_SIZE 256u
#define UART_TX_DMA_BUFFER_SIZE 256u
#define UART_RX_RING_BUFFER_SIZE 512u
#define UART_TX_RING_BUFFER_SIZE 384u
#define UART_DEFAULT_BAUDRATE 115200u
typedef struct {