feat(ch390): optimize SPI transfer, MAC fallback, and build settings for V1.0.0

- increase UART DMA/ring buffer sizes for mux traffic
- switch SPI1 to Mode0 with prescaler /2 and align CubeMX settings
- refactor CH390 memory read/write path with chunked SPI read and HAL bulk write
- fallback to hardware MAC when configured MAC is invalid (all-zero)
- add mux frame RTT logs and remove redundant UART1 polling
- update Keil post-build viewer integration and include build viewer artifacts
- update AT manual with all-zero MAC behavior

Core/Src/main.c

@@ -57,7 +57,6 @@ void SystemClock_Config(void);
 static void LED_Init(void);
 static void LED_StartBlink(void);
 static void BootDiag_ReportCh390(void);
-static void App_PollUart1ConfigRx(void);
 static void App_Init(void);
 static void App_Poll(void);
 static void App_ConfigureLinks(const device_config_t *cfg);
@@ -143,14 +142,6 @@ static void BootDiag_ReportCh390(void)
                       cfg->mux_mode);
 }
 
-static void App_PollUart1ConfigRx(void)
-{
-    while (__HAL_UART_GET_FLAG(&huart1, UART_FLAG_RXNE) != RESET) {
-        uint8_t byte = (uint8_t)(huart1.Instance->DR & 0xFFu);
-        config_uart_rx_byte(byte);
-    }
-}
-
 static void App_ConfigureLinks(const device_config_t *cfg)
 {
     tcp_server_instance_config_t server_cfg;
@@ -352,6 +343,7 @@ static void App_RouteMuxUartTraffic(void)
     const device_config_t *cfg = config_get();
 
     while (uart_mux_try_extract_frame(UART_CHANNEL_U0, &frame)) {
+        SEGGER_RTT_printf(0, "Mux frame from UART0: src_id=%u dst_mask=0x%02X len=%u\r\n", frame.src_id, frame.dst_mask, frame.payload_len);
         if (frame.dst_mask == 0u) {
             at_result_t result;
             char *response_text = (char *)&g_mux_response_frame[5];
@@ -390,6 +382,7 @@ static void App_RouteMuxUartTraffic(void)
     }
 
     while (uart_mux_try_extract_frame(UART_CHANNEL_U1, &frame)) {
+        SEGGER_RTT_printf(0, "Mux frame from UART1: src_id=%u dst_mask=0x%02X len=%u\r\n", frame.src_id, frame.dst_mask, frame.payload_len);
         if (frame.dst_mask == 0u) {
             at_result_t result;
             char *response_text = (char *)&g_mux_response_frame[5];
@@ -437,7 +430,6 @@ static void App_Poll(void)
     App_StartLinksIfNeeded();
     tcp_client_poll();
     uart_trans_poll();
-    App_PollUart1ConfigRx();
     StackGuard_Check();
     config_poll();
     App_RouteTcpTraffic();

Core/Src/spi.c

@@ -44,7 +44,7 @@ void MX_SPI1_Init(void)
   hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;    /* Match CH390 runtime baseline: CPOL=Low */
   hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;        /* Match CH390 runtime baseline: CPHA=1Edge (Mode 0) */
   hspi1.Init.NSS = SPI_NSS_SOFT;                /* Software CS control for CH390 */
-  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64; /* 72MHz/64 = 1.125MHz for conservative CH390 bring-up */
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; /* 72MHz/2 = 36MHz, max SPI1 clock at current APB2 */
   hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
   hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
   hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;