feat(ch390): optimize SPI transfer, MAC fallback, and build settings for V1.0.0

- increase UART DMA/ring buffer sizes for mux traffic
- switch SPI1 to Mode0 with prescaler /2 and align CubeMX settings
- refactor CH390 memory read/write path with chunked SPI read and HAL bulk write
- fallback to hardware MAC when configured MAC is invalid (all-zero)
- add mux frame RTT logs and remove redundant UART1 polling
- update Keil post-build viewer integration and include build viewer artifacts
- update AT manual with all-zero MAC behavior
This commit is contained in:
2026-04-05 03:47:54 +08:00
parent c5b2bdd2d2
commit efb88ea367
11 changed files with 143 additions and 41 deletions
+33 -16
View File
@@ -60,6 +60,7 @@ extern SPI_HandleTypeDef hspi1;
/* Timeout for SPI operations (ms) */
#define SPI_TIMEOUT 100
#define CH390_SPI_CHUNK_SIZE 64u
/*----------------------------------------------------------------------------
* Low-level GPIO operations
@@ -105,6 +106,24 @@ static uint8_t ch390_spi_exchange_byte(uint8_t byte)
return rx_data;
}
static int ch390_spi_read_bytes(uint8_t *data, uint16_t length)
{
static const uint8_t dummy_tx[CH390_SPI_CHUNK_SIZE] = {0};
while (length > 0u)
{
uint16_t chunk = (length > CH390_SPI_CHUNK_SIZE) ? CH390_SPI_CHUNK_SIZE : length;
if (HAL_SPI_TransmitReceive(&hspi1, (uint8_t *)dummy_tx, data, chunk, SPI_TIMEOUT) != HAL_OK)
{
return -1;
}
data += chunk;
length = (uint16_t)(length - chunk);
}
return 0;
}
static void ch390_spi_apply_mode(uint32_t polarity, uint32_t phase)
{
hspi1.Init.CLKPolarity = polarity;
@@ -281,16 +300,15 @@ void ch390_write_reg(uint8_t reg, uint8_t value)
*/
void ch390_read_mem(uint8_t *data, int length)
{
int i;
if (data == NULL || length <= 0)
{
return;
}
ch390_cs(0); /* CS low - select */
ch390_spi_exchange_byte(OPC_MEM_READ); /* Send memory read command */
/* Read data bytes */
for (i = 0; i < length; i++)
{
data[i] = ch390_spi_dummy_read();
}
(void)ch390_spi_read_bytes(data, (uint16_t)length);
ch390_cs(1); /* CS high - deselect */
}
@@ -322,16 +340,15 @@ void ch390_read_mem_dma(uint8_t *data, int length)
*/
void ch390_write_mem(uint8_t *data, int length)
{
int i;
if (data == NULL || length <= 0)
{
return;
}
ch390_cs(0); /* CS low - select */
ch390_spi_exchange_byte(OPC_MEM_WRITE); /* Send memory write command */
/* Write data bytes */
for (i = 0; i < length; i++)
{
ch390_spi_exchange_byte(data[i]);
}
(void)HAL_SPI_Transmit(&hspi1, data, (uint16_t)length, SPI_TIMEOUT);
ch390_cs(1); /* CS high - deselect */
}
+26 -1
View File
@@ -157,6 +157,19 @@ struct pbuf *ch390_runtime_input_frame(struct netif *netif)
return p;
}
bool ch390_mac_address_valid(const uint8_t *mac)
{
if (mac == NULL) {
return false;
}
for (uint8_t i = 0; i < ETHARP_HWADDR_LEN; ++i) {
if (mac[i] == 0u) {
return false;
}
}
return true;
}
void ch390_runtime_init(struct netif *netif, const uint8_t *mac)
{
struct ethernetif *ethernetif = (struct ethernetif *)netif->state;
@@ -186,7 +199,19 @@ void ch390_runtime_init(struct netif *netif, const uint8_t *mac)
SEGGER_RTT_WriteString(0, "ETH init: default\r\n");
ch390_default_config();
SEGGER_RTT_WriteString(0, "ETH init: mac\r\n");
ch390_set_mac_address((uint8_t *)mac);
if (ch390_mac_address_valid(mac)) {
ch390_set_mac_address((uint8_t *)mac);
}
else {
if (mac != NULL) {
ch390_get_mac((uint8_t *)mac);
SEGGER_RTT_printf(0, "ETH init: invalid MAC in config, using hardware MAC: %02X:%02X:%02X:%02X:%02X:%02X\r\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
}
else {
SEGGER_RTT_WriteString(0, "ETH init: no MAC in config\r\n");
}
}
netif->hwaddr_len = ETHARP_HWADDR_LEN;
SEGGER_RTT_WriteString(0, "ETH init: getmac\r\n");