feat(ch390): optimize SPI transfer, MAC fallback, and build settings for V1.0.0
- increase UART DMA/ring buffer sizes for mux traffic - switch SPI1 to Mode0 with prescaler /2 and align CubeMX settings - refactor CH390 memory read/write path with chunked SPI read and HAL bulk write - fallback to hardware MAC when configured MAC is invalid (all-zero) - add mux frame RTT logs and remove redundant UART1 polling - update Keil post-build viewer integration and include build viewer artifacts - update AT manual with all-zero MAC behavior
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@@ -60,6 +60,7 @@ extern SPI_HandleTypeDef hspi1;
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/* Timeout for SPI operations (ms) */
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#define SPI_TIMEOUT 100
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#define CH390_SPI_CHUNK_SIZE 64u
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/*----------------------------------------------------------------------------
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* Low-level GPIO operations
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@@ -105,6 +106,24 @@ static uint8_t ch390_spi_exchange_byte(uint8_t byte)
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return rx_data;
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}
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static int ch390_spi_read_bytes(uint8_t *data, uint16_t length)
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{
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static const uint8_t dummy_tx[CH390_SPI_CHUNK_SIZE] = {0};
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while (length > 0u)
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{
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uint16_t chunk = (length > CH390_SPI_CHUNK_SIZE) ? CH390_SPI_CHUNK_SIZE : length;
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if (HAL_SPI_TransmitReceive(&hspi1, (uint8_t *)dummy_tx, data, chunk, SPI_TIMEOUT) != HAL_OK)
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{
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return -1;
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}
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data += chunk;
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length = (uint16_t)(length - chunk);
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}
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return 0;
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}
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static void ch390_spi_apply_mode(uint32_t polarity, uint32_t phase)
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{
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hspi1.Init.CLKPolarity = polarity;
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@@ -281,16 +300,15 @@ void ch390_write_reg(uint8_t reg, uint8_t value)
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*/
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void ch390_read_mem(uint8_t *data, int length)
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{
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int i;
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if (data == NULL || length <= 0)
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{
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return;
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}
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ch390_cs(0); /* CS low - select */
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ch390_spi_exchange_byte(OPC_MEM_READ); /* Send memory read command */
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/* Read data bytes */
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for (i = 0; i < length; i++)
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{
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data[i] = ch390_spi_dummy_read();
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}
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(void)ch390_spi_read_bytes(data, (uint16_t)length);
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ch390_cs(1); /* CS high - deselect */
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}
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@@ -322,16 +340,15 @@ void ch390_read_mem_dma(uint8_t *data, int length)
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*/
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void ch390_write_mem(uint8_t *data, int length)
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{
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int i;
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if (data == NULL || length <= 0)
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{
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return;
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}
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ch390_cs(0); /* CS low - select */
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ch390_spi_exchange_byte(OPC_MEM_WRITE); /* Send memory write command */
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/* Write data bytes */
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for (i = 0; i < length; i++)
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{
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ch390_spi_exchange_byte(data[i]);
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}
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(void)HAL_SPI_Transmit(&hspi1, data, (uint16_t)length, SPI_TIMEOUT);
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ch390_cs(1); /* CS high - deselect */
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}
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@@ -157,6 +157,19 @@ struct pbuf *ch390_runtime_input_frame(struct netif *netif)
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return p;
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}
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bool ch390_mac_address_valid(const uint8_t *mac)
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{
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if (mac == NULL) {
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return false;
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}
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for (uint8_t i = 0; i < ETHARP_HWADDR_LEN; ++i) {
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if (mac[i] == 0u) {
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return false;
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}
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}
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return true;
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}
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void ch390_runtime_init(struct netif *netif, const uint8_t *mac)
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{
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struct ethernetif *ethernetif = (struct ethernetif *)netif->state;
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@@ -186,7 +199,19 @@ void ch390_runtime_init(struct netif *netif, const uint8_t *mac)
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SEGGER_RTT_WriteString(0, "ETH init: default\r\n");
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ch390_default_config();
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SEGGER_RTT_WriteString(0, "ETH init: mac\r\n");
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ch390_set_mac_address((uint8_t *)mac);
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if (ch390_mac_address_valid(mac)) {
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ch390_set_mac_address((uint8_t *)mac);
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}
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else {
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if (mac != NULL) {
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ch390_get_mac((uint8_t *)mac);
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SEGGER_RTT_printf(0, "ETH init: invalid MAC in config, using hardware MAC: %02X:%02X:%02X:%02X:%02X:%02X\r\n",
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mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
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}
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else {
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SEGGER_RTT_WriteString(0, "ETH init: no MAC in config\r\n");
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}
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}
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netif->hwaddr_len = ETHARP_HWADDR_LEN;
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SEGGER_RTT_WriteString(0, "ETH init: getmac\r\n");
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