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fix: restore CH390 bridge flow and sync driver docs

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2026-04-03 05:18:02 +08:00
parent 1ef1ba9490
commit fd1fae8ad7
18 changed files with 501 additions and 178 deletions
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Drivers/CH390/CH390_Interface.c
+6 -29
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@@ -86,23 +86,6 @@ static inline void ch390_rst(uint8_t state)
state ? GPIO_PIN_SET : GPIO_PIN_RESET);
}
static inline void ch390_sck(uint8_t state)
{
HAL_GPIO_WritePin(CH390_SCK_PORT, CH390_SCK_PIN,
state ? GPIO_PIN_SET : GPIO_PIN_RESET);
}
static inline void ch390_mosi(uint8_t state)
{
HAL_GPIO_WritePin(CH390_MOSI_PORT, CH390_MOSI_PIN,
state ? GPIO_PIN_SET : GPIO_PIN_RESET);
}
static inline uint8_t ch390_miso(void)
{
return (uint8_t)(HAL_GPIO_ReadPin(CH390_MISO_PORT, CH390_MISO_PIN) == GPIO_PIN_SET);
}
/*----------------------------------------------------------------------------
* SPI Communication
*---------------------------------------------------------------------------*/
@@ -197,11 +180,9 @@ void ch390_interrupt_init(void)
void ch390_spi_init(void)
{
/* SPI1 is initialized by MX_SPI1_Init() in main.c */
/* We need to ensure correct SPI mode for CH390: */
/* - CPOL = High (idle clock is high) */
/* - CPHA = 2Edge (data captured on second edge) */
ch390_spi_apply_mode(SPI_POLARITY_LOW, SPI_PHASE_1EDGE); /* Start with Mode 0 */
/* Reference CH390 SPI path uses mode 3. */
ch390_spi_apply_mode(SPI_POLARITY_HIGH, SPI_PHASE_2EDGE);
SEGGER_RTT_WriteString(0, "CH390 SPI mode=3 (CPOL=1 CPHA=1)\r\n");
}
/**
@@ -252,7 +233,7 @@ void ch390_delay_us(uint32_t time)
*/
void ch390_hardware_reset(void)
{
ch390_delay_us(3000); /* Short delay before reset */
ch390_delay_us(10000); /* Short delay before reset */
ch390_rst(0); /* Assert reset (low) */
ch390_delay_us(3000); /* Hold reset for 3ms to satisfy datasheet minimum */
ch390_rst(1); /* Release reset (high) */
@@ -287,13 +268,9 @@ uint8_t ch390_read_reg(uint8_t reg)
*/
void ch390_write_reg(uint8_t reg, uint8_t value)
{
uint8_t frame[2];
frame[0] = reg | OPC_REG_W;
frame[1] = value;
ch390_cs(0); /* CS low - select */
ch390_spi_exchange_byte(frame[0]); /* Send write command */
ch390_spi_exchange_byte(frame[1]); /* Send write data */
(void)ch390_spi_exchange_byte(reg | OPC_REG_W);
(void)ch390_spi_exchange_byte(value);
ch390_cs(1); /* CS high - deselect */
}