chore: update Keil project files and build record for V1.0.1

根因: tcp_close()将对端关闭的pcb推入TIME_WAIT(120s), 占用MEMP_TCP_PCB池(仅4个),
多连接同时断开后pcb池耗尽, tcp_new()返回NULL, 新连接无法建立直到120s超时释放。

核心修复:
- tcp_server/client: 对端关闭(p=NULL)时tcp_abort替代tcp_close, pcb立即释放
- ch390_runtime: PKT_ERR恢复强制OR上RCR_RXEN(与WCH官方一致)
- ch390_runtime: TX连续超时3次自动emergency reset
- ch390_runtime: 每5秒health_check读VID验证芯片存活
- main: App_StartLinksIfNeeded失败时不标记g_links_started, 允许重试
- main: MUX逐帧RTT printf改为#if DEBUG门控, 减少主循环延迟
- uart_trans: MUX帧解析改为先搜0x7E再消费header, 非法帧只丢1字节

.debug/uart-ch390-debug-handoff.md

@@ -0,0 +1,174 @@
+# TCP2UART Debug Handoff
+
+## Scope
+
+This log records the debugging work completed so far for:
+
+- UART1 config/debug path on `COM9`
+- UART2/UART3 transparent UART paths on `COM8`/`COM7`
+- CH390 and lwIP bring-up status
+
+The goal is to preserve the usable conclusions and avoid repeating invalid test paths after context cleanup.
+
+## Final State Summary
+
+### Confirmed working
+
+- HSE clock path is working on the current board/chip/crystal combination.
+- ST-Link + RTT debugging works.
+- Firmware boots and RTT shows stable startup output.
+- UART2 and UART3 TX paths were validated earlier by host-side observation:
+  - `COM8` receives UART2 debug output.
+  - `COM7` receives UART3 debug output.
+- UART1 config path is working in the current cleaned firmware when the host sends commands with a line ending that the parser actually consumes.
+- `AT+?` over UART1 was successfully validated when sent with `\n`.
+
+### Confirmed not yet working
+
+- CH390 is still not operating normally.
+- Current one-shot RTT report still shows abnormal values:
+  - `CH390 VID=0x3A3A PID=0xCCCC REV=0x00 NSR=0x00 LINK=0`
+- Therefore lwIP / Ethernet / TCP end-to-end validation remains blocked by CH390 low-level failure.
+
+## Most Important Lessons Learned
+
+### 1. UART1 config failures were partly test-method failures
+
+Several earlier negative conclusions about UART1 config were caused by the debug method rather than firmware defects.
+
+Examples:
+
+- Sending `AT+?` without the line ending expected by the current parser caused false negatives.
+- Frequent open/close cycles on the serial port changed timing and control-line behavior.
+- Breakpoints in RX callback / parser code prevented reply transmission and created false "no response" results.
+- Heavy RTT logging inside hot UART paths distorted timing and even corrupted RTT control state once.
+
+### 2. UART1 parser expects terminators
+
+`config_uart_rx_byte()` only dispatches a command when it sees `\r` or `\n`.
+
+Successful command form that was confirmed:
+
+```text
+AT+?\n
+```
+
+Do not assume `AT+?` without line ending is valid for this firmware.
+
+### 3. Cleaned firmware state is preferable for future work
+
+Temporary UART diagnostics were removed again after debugging:
+
+- removed boot markers like `BOOT_UARTx_OK`
+- removed periodic UART spam
+- removed UART1 byte echo
+- removed temporary `config_diag` counters
+
+Useful RTT remains:
+
+- `TCP2UART boot`
+- HSE fallback warning if used
+- CH390 one-shot status report
+
+## Relevant Code Changes Left In Place
+
+These are intentional and should remain unless there is a specific reason to change them.
+
+### UART1 config path
+
+- `App/config.c`
+  - config handle is back on `huart1`
+  - `config_uart_rx_byte()` assembles frames from UART1 bytes
+  - `config_poll()` dispatches a pending complete frame to `config_try_process_frame()`
+  - `config_try_process_frame()` calls `config_process_at_cmd()` and transmits the response on UART1
+
+- `Core/Src/stm32f1xx_it.c`
+  - `HAL_UART_RxCpltCallback()` for `huart1` feeds the received byte into `config_uart_rx_byte()` and rearms `HAL_UART_Receive_IT()`
+
+### RTT boot diagnostics
+
+- `Core/Src/main.c`
+  - retains RTT boot banner
+  - retains one-shot CH390 report
+  - no temporary UART spam remains
+
+## Current Firmware Behavior Worth Remembering
+
+### UART1
+
+- UART1 is used for config/debug interaction.
+- UART1 parser is line-oriented.
+- Use a terminal that sends `LF` or `CRLF` explicitly.
+
+### UART2 / UART3
+
+- UART2 and UART3 are for bridge channels, not the config path.
+- Earlier mapping observed during testing:
+  - `COM8` aligned with UART2 TX activity
+  - `COM7` aligned with UART3 TX activity
+
+### CH390
+
+- Still unresolved at the low level.
+- Do not spend time on lwIP / TCP behavior until CH390 register reads look sane.
+
+## Recommended Next Debug Order
+
+### Priority 1: Preserve UART1 config as known-good
+
+Before touching UART1 code again:
+
+1. Open `COM9` at `115200 8N1`
+2. Send:
+
+```text
+AT+?\n
+```
+
+3. Confirm a full config dump is returned.
+
+If this fails again, check the terminal's actual line ending first before changing code.
+
+### Priority 2: Re-verify UART2/UART3 only if needed
+
+If bridge debugging resumes, first confirm the host can actually open `COM7` and `COM8`.
+Host-side availability was inconsistent during the previous session and caused false negatives.
+
+### Priority 3: Resume CH390 low-level debugging
+
+This is the real remaining blocker.
+
+Suggested next steps:
+
+1. Focus on SPI-level sanity before lwIP.
+2. Re-check CH390 reset / CS / SPI timing and electrical path.
+3. Verify whether SPI mode is correct for the actual hardware.
+4. Confirm register reads from CH390 return plausible values before attempting link/TCP tests.
+
+## What Not To Repeat
+
+- Do not judge UART1 config by sending commands without a terminator.
+- Do not leave breakpoints inside UART RX callback or parser while expecting normal replies.
+- Do not flood RTT inside hot UART receive paths.
+- Do not conclude lwIP is broken before CH390 identity reads are sane.
+- Do not trust `Win32_SerialPort` alone for COM availability; sometimes `mode COMx` / `Get-PnpDevice -Class Ports` gives a different picture.
+
+## Known Useful Commands
+
+### UART1 config test
+
+```text
+AT+?\n
+```
+
+### Optional follow-ups
+
+```text
+AT+BAUD1=115200\n
+AT+SAVE\n
+AT+RESET\n
+```
+
+## One-Line Handoff
+
+UART1 config is working when tested correctly with a terminator; CH390 is still the unresolved core issue and should be the next serious debug target.

.gitignore

@@ -7,6 +7,7 @@
 *.map
 *.lst
 *.out
+*.log
 
 # IDE
 .vscode/
@@ -27,6 +28,9 @@ Release/
 MDK-ARM/DebugConfig/
 MDK-ARM/TCP2UART/
 
+# CMake build
+build/
+
 # OS
 Thumbs.db
 Desktop.ini
@@ -34,3 +38,9 @@ Desktop.ini
 
 # 项目文档
 项目计划.md
+
+# Local debug handoff logs
+.debug/
+
+# Local packet captures
+WiresharkLog/

AT固件使用手册.md

@@ -0,0 +1,389 @@
+# TCP2UART AT 固件使用手册
+
+## 1. 文档范围
+
+本文档定义 `TCP2UART` 项目的最终 AT 外部协议。
+
+本文档只描述最终协议模型，不保留任何历史展开式实例字段，不包含测试记录，不讨论旧版兼容命令。
+
+适用对象：
+
+- 上位机开发人员
+- 联调与测试人员
+- 固件接口实现人员
+
+## 2. 设备与接口
+
+- 主控：`STM32F103R8T6`
+- 以太网芯片：`CH390D`
+- 配置口：`USART1`
+- 数据口：`USART2`、`USART3`
+
+职责划分：
+
+- `USART1`：AT 配置口
+- `USART2 / USART3`：业务数据口，可工作于普通透传或 MUX 透传模式
+
+## 3. 最终协议模型
+
+本项目最终控制协议由三部分组成：
+
+1. `MUX`：全局数据承载模式开关
+2. `NET`：全局静态网络配置记录
+3. `LINK[ROLE]`：按角色名组织的链路配置记录（`S1/S2/C1/C2`）
+
+约束如下：
+
+- 设备只有一张网卡，因此本地网络参数只配置一次
+- DHCP 不属于最终协议范围
+- 所有 AT 文本命令必须以 `\r\n` 结尾
+- 当 `DSTMASK=0x00` 时，MUX 数据口中的系统控制帧进入 AT 解析路径，其控制文本同样必须以 `\r\n` 结尾
+
+## 4. MUX 帧格式
+
+当 `MUX=1` 时，数据口使用如下帧格式：
+
+```text
+SYNC | LEN_H | LEN_L | SRCID | DSTMASK | PAYLOAD | TAIL
+```
+
+字段定义：
+
+- `SYNC`：帧起始标记，建议固定为 `0x7E`
+- `LEN_H / LEN_L`：`PAYLOAD` 长度，高字节在前
+- `SRCID`：单字节源端点 ID
+- `DSTMASK`：单字节目标端点位图
+- `PAYLOAD`：负载数据
+- `TAIL`：帧结束标记，建议固定为 `0x7F`
+
+规则：
+
+- `DSTMASK != 0x00`：业务数据帧
+- `DSTMASK = 0x00`：系统控制帧
+- 系统控制帧的 `PAYLOAD` 为 AT 文本，必须以 `\r\n` 结束
+
+## 5. 统一端点编码
+
+`UART` 与 `TCP` 逻辑实例统一进入同一套编码空间：
+
+| 端点 | 编码 |
+|------|------|
+| `C1` | `0x01` |
+| `C2` | `0x02` |
+| `UART2` | `0x04` |
+| `UART3` | `0x08` |
+| `S1` | `0x10` |
+| `S2` | `0x20` |
+
+说明：
+
+- `SRCID` 必须为单一端点值
+- `DSTMASK` 可以是一个或多个端点编码按位或的结果
+- `DSTMASK=0x00` 保留给系统控制帧
+
+## 6. AT 命令总则
+
+### 6.1 命令结尾
+
+所有 AT 命令均必须以 `\r\n` 结尾。
+
+例如：
+
+```text
+AT\r\n
+AT+MUX?\r\n
+AT+NET=192.168.1.100,255.255.255.0,192.168.1.1,02:00:00:00:00:01\r\n
+```
+
+### 6.2 持久化规则
+
+参数设置成功后只写入当前运行配置，不会自动写入 Flash。
+
+若要掉电保持，必须执行：
+
+1. `AT+SAVE\r\n`
+2. `AT+RESET\r\n`
+
+### 6.3 响应风格
+
+- 成功：`OK`
+- 需要保存后生效时，允许追加提示文本
+- 失败：`ERROR: <reason>`
+
+## 7. 默认配置
+
+### 7.1 MUX 默认值
+
+```text
+MUX = 0
+```
+
+### 7.2 NET 默认值
+
+```text
+NET = 192.168.1.100,255.255.255.0,192.168.1.1,02:00:00:00:00:01
+```
+
+### 7.3 LINK 默认值
+
+```text
+LINK:S1 = 1,8080,0.0.0.0,0,U0
+LINK:S2 = 0,8081,0.0.0.0,0,U1
+LINK:C1 = 1,9001,192.168.1.200,9000,U1
+LINK:C2 = 0,9002,192.168.1.201,9001,U0
+```
+
+说明：
+
+- `S1/S2/C1/C2` 为对外可见角色名
+- 内部索引映射由固件管理，不对外暴露
+
+UART 记号约定：
+
+- `U0 = USART2`
+- `U1 = USART3`
+
+## 8. AT 命令定义
+
+### 8.1 测试设备在线
+
+命令：
+
+```text
+AT\r\n
+```
+
+返回：
+
+```text
+OK
+```
+
+### 8.2 查询摘要
+
+命令：
+
+```text
+AT+?\r\n
+AT+QUERY\r\n
+```
+
+推荐返回格式：
+
+```text
++NET:IP=192.168.1.100,MASK=255.255.255.0,GW=192.168.1.1,MAC=02:00:00:00:00:01
++LINK:S1,EN=1,LPORT=8080,RIP=0.0.0.0,RPORT=0,UART=U0
++LINK:S2,EN=0,LPORT=8081,RIP=0.0.0.0,RPORT=0,UART=U1
++LINK:C1,EN=1,LPORT=9001,RIP=192.168.1.200,RPORT=9000,UART=U1
++LINK:C2,EN=0,LPORT=9002,RIP=192.168.1.201,RPORT=9001,UART=U0
++MUX:0
++MAP:UART2=0x04,UART3=0x08,C1=0x01,C2=0x02,S1=0x10,S2=0x20
++BAUD:U0=115200,U1=115200
+OK
+```
+
+### 8.3 MUX 类命令
+
+#### 设置 MUX
+
+```text
+AT+MUX=1\r\n
+```
+
+参数：
+
+- `0`：普通透传模式
+- `1`：MUX 透传模式
+
+查询：
+
+```text
+AT+MUX?\r\n
+```
+
+返回示例：
+
+```text
++MUX:1
+OK
+```
+
+### 8.4 NET 类命令
+
+#### 设置 NET
+
+```text
+AT+NET=192.168.1.100,255.255.255.0,192.168.1.1,02:00:00:00:00:01\r\n
+```
+
+字段顺序：
+
+```text
+IP,MASK,GW,MAC
+```
+
+查询：
+
+```text
+AT+NET?\r\n
+```
+
+返回示例：
+
+```text
++NET:IP=192.168.1.100,MASK=255.255.255.0,GW=192.168.1.1,MAC=02:00:00:00:00:01
+OK
+```
+
+**MAC 设置说明：**
+
+当MAC设置为全0时，固件将使用硬件MAC地址，此时通过AT+?查询到的MAC地址即为当前生效的硬件MAC地址。
+
+### 8.5 LINK 类命令
+
+#### 设置单条 LINK 记录
+
+```text
+AT+LINK=S1,1,8080,0.0.0.0,0,U0\r\n
+AT+LINK=C1,1,9001,192.168.1.200,9000,U1\r\n
+```
+
+字段顺序：
+
+```text
+ROLE,EN,LPORT,RIP,RPORT,UART
+```
+
+字段说明：
+
+- `ROLE`：链路角色名，固定为 `S1/S2/C1/C2`
+- `EN`：`0/1`
+- `LPORT`：本地端口
+- `RIP`：对端 IP
+- `RPORT`：对端端口
+- `UART`：`U0/U1`
+
+说明：
+
+- `Server` 与 `Client` 共用同一条 `LINK` 记录模型
+- `Server` 中 `RIP/RPORT` 可作为允许接入的对端约束或预设对端信息
+- `Client` 中 `RIP/RPORT` 表示远端目标地址与端口
+
+#### 查询单条 LINK
+
+```text
+AT+LINK=S1\r\n
+```
+
+返回示例：
+
+```text
++LINK:S1,EN=1,LPORT=8080,RIP=0.0.0.0,RPORT=0,UART=U0
+OK
+```
+
+#### 查询全部 LINK
+
+```text
+AT+LINK?\r\n
+```
+
+返回示例：
+
+```text
++LINK:S1,EN=1,LPORT=8080,RIP=0.0.0.0,RPORT=0,UART=U0
++LINK:S2,EN=0,LPORT=8081,RIP=0.0.0.0,RPORT=0,UART=U1
++LINK:C1,EN=1,LPORT=9001,RIP=192.168.1.200,RPORT=9000,UART=U1
++LINK:C2,EN=0,LPORT=9002,RIP=192.168.1.201,RPORT=9001,UART=U0
+OK
+```
+
+## 9. 保存与复位命令
+
+### 9.1 保存配置
+
+```text
+AT+SAVE\r\n
+```
+
+成功返回：
+
+```text
+OK: Configuration saved
+```
+
+### 9.2 软件复位
+
+```text
+AT+RESET\r\n
+```
+
+返回：
+
+```text
+OK: Resetting...
+```
+
+### 9.3 恢复默认值
+
+```text
+AT+DEFAULT\r\n
+```
+
+返回：
+
+```text
+OK: Defaults restored
+```
+
+## 10. 常见错误返回
+
+| 场景 | 返回 |
+|------|------|
+| 未知命令 | `ERROR: Unknown command` |
+| 非法端口 | `ERROR: Invalid port` |
+| 非法波特率 | `ERROR: Invalid baudrate` |
+| 非法 IP 地址 | `ERROR: Invalid IP format` |
+| 非法掩码 | `ERROR: Invalid mask format` |
+| 非法网关 | `ERROR: Invalid gateway format` |
+| 非法远端 IP | `ERROR: Invalid remote IP format` |
+| 非法 MAC | `ERROR: Invalid MAC format` |
+| 非法 `SRCID` / `DSTMASK` | `ERROR: Invalid route field` |
+| Flash 保存失败 | `ERROR: Save failed` |
+
+## 11. 推荐配置流程
+
+```text
+AT+NET=192.168.1.123,255.255.255.0,192.168.1.1,02:00:00:00:00:01\r\n
+AT+LINK=S1,1,10001,0.0.0.0,0,U1\r\n
+AT+LINK=S2,1,10003,0.0.0.0,0,U1\r\n
+AT+LINK=C1,1,20001,192.168.1.201,10002,U0\r\n
+AT+MUX=1\r\n
+AT+SAVE\r\n
+AT+RESET\r\n
+```
+
+## 12. 故障排查建议
+
+### 12.1 发送 `AT` 没有返回
+
+优先检查：
+
+1. 是否连接到 `USART1`
+2. 串口参数是否为 `115200 8N1`
+3. 是否严格使用 `\r\n` 作为命令结尾
+4. 接线是否正确
+5. 设备是否正常上电运行
+
+### 12.2 设置成功但重启后参数丢失
+
+检查是否漏掉以下步骤：
+
+1. `AT+SAVE\r\n`
+2. `AT+RESET\r\n`
+
+## 13. 相关文件
+
+- AT 命令实现：[config.c](/D:/code/STM32Project/TCP2UART/App/config.c)
+- 配置结构与默认值：[config.h](/D:/code/STM32Project/TCP2UART/App/config.h)
+- 调试与测试记录：[uart-ch390-debug-handoff.md](/D:/code/STM32Project/TCP2UART/uart-ch390-debug-handoff.md)

App/config.h

@@ -1,96 +1,78 @@
 /**
  * @file config.h
- * @brief AT command configuration module for TCP2UART
- * 
- * Handles UART1 AT commands for network and serial port configuration.
- * 
- * Supported AT commands:
- * - AT+IP=192.168.1.100       Set device IP
- * - AT+MASK=255.255.255.0     Set subnet mask
- * - AT+GW=192.168.1.1         Set gateway
- * - AT+PORT=8080              Set TCP Server listen port
- * - AT+RIP=192.168.1.200      Set TCP Client remote IP
- * - AT+RPORT=9000             Set TCP Client remote port
- * - AT+BAUD1=115200           Set UART2 baudrate
- * - AT+BAUD2=115200           Set UART3 baudrate
- * - AT+MAC=00:11:22:33:44:55  Set MAC address
- * - AT+DHCP=0/1               Enable/disable DHCP
- * - AT+SAVE                   Save parameters to Flash
- * - AT+RESET                  Reset device
- * - AT+DEFAULT                Restore factory defaults
- * - AT+?                      Query current configuration
+ * @brief Final AT configuration model for TCP2UART.
  */
 
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#include <stdint.h>
 #include <stdbool.h>
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/* Configuration magic number "TCPU" */
-#define CONFIG_MAGIC            0x54435055
+#define CONFIG_MAGIC             0x54435055u
+#define CONFIG_VERSION           0x0003u
 
-/* Configuration version for compatibility */
-#define CONFIG_VERSION          0x0001
+#define CONFIG_UART_COUNT        2u
+#define CONFIG_LINK_COUNT        4u
+
+#define CONFIG_LINK_S1           0u
+#define CONFIG_LINK_S2           1u
+#define CONFIG_LINK_C1           2u
+#define CONFIG_LINK_C2           3u
+
+#define ENDPOINT_C1              0x01u
+#define ENDPOINT_C2              0x02u
+#define ENDPOINT_UART2           0x04u
+#define ENDPOINT_UART3           0x08u
+#define ENDPOINT_S1              0x10u
+#define ENDPOINT_S2              0x20u
+
+#define LINK_UART_U0             0u
+#define LINK_UART_U1             1u
+
+typedef enum {
+    MUX_MODE_RAW = 0,
+    MUX_MODE_FRAME = 1
+} mux_mode_t;
 
-/* Device configuration structure */
 typedef struct {
-    uint32_t magic;             /* Magic number for validation */
-    uint16_t version;           /* Configuration version */
-    uint16_t reserved;          /* Reserved for alignment */
+    uint8_t ip[4];
+    uint8_t mask[4];
+    uint8_t gw[4];
+    uint8_t mac[6];
+    uint8_t reserved[2];
+} net_config_t;
 
-    /* Network settings */
-    uint8_t  mac[6];            /* MAC address */
-    uint8_t  dhcp_enable;       /* DHCP enable flag */
-    uint8_t  reserved2;         /* Reserved for alignment */
-    uint8_t  ip[4];             /* Device IP address */
-    uint8_t  mask[4];           /* Subnet mask */
-    uint8_t  gw[4];             /* Gateway */
+typedef struct {
+    uint8_t enabled;
+    uint8_t uart;
+    uint16_t local_port;
+    uint8_t remote_ip[4];
+    uint16_t remote_port;
+    uint16_t reserved;
+} link_config_t;
 
-    /* TCP Server settings */
-    uint16_t server_port;       /* Server listen port */
-    uint16_t reserved3;         /* Reserved for alignment */
-    
-    /* TCP Client settings */
-    uint8_t  remote_ip[4];      /* Remote server IP */
-    uint16_t remote_port;       /* Remote server port */
-    uint16_t reconnect_interval;/* Reconnect interval (ms) */
-    
-    /* UART settings */
-    uint32_t uart2_baudrate;    /* UART2 (Server) baudrate */
-    uint32_t uart3_baudrate;    /* UART3 (Client) baudrate */
-    uint8_t  uart2_databits;    /* UART2 data bits */
-    uint8_t  uart2_stopbits;    /* UART2 stop bits */
-    uint8_t  uart2_parity;      /* UART2 parity */
-    uint8_t  uart3_databits;    /* UART3 data bits */
-    uint8_t  uart3_stopbits;    /* UART3 stop bits */
-    uint8_t  uart3_parity;      /* UART3 parity */
-    uint16_t reserved4;         /* Reserved for alignment */
-    
-    /* CRC32 checksum (must be last) */
+typedef struct {
+    uint32_t magic;
+    uint16_t version;
+    uint8_t mux_mode;
+    uint8_t reserved0;
+    net_config_t net;
+    link_config_t links[CONFIG_LINK_COUNT];
+    uint32_t uart_baudrate[CONFIG_UART_COUNT];
     uint32_t crc;
 } device_config_t;
 
-/* Default configuration values */
-#define DEFAULT_IP              {192, 168, 1, 100}
-#define DEFAULT_MASK            {255, 255, 255, 0}
-#define DEFAULT_GW              {192, 168, 1, 1}
-#define DEFAULT_MAC             {0x02, 0x00, 0x00, 0x00, 0x00, 0x01}
-#define DEFAULT_SERVER_PORT     8080
-#define DEFAULT_REMOTE_IP       {192, 168, 1, 200}
-#define DEFAULT_REMOTE_PORT     9000
-#define DEFAULT_UART_BAUDRATE   115200
-#define DEFAULT_UART_DATABITS   8
-#define DEFAULT_UART_STOPBITS   1
-#define DEFAULT_UART_PARITY     0
-#define DEFAULT_DHCP_ENABLE     0
-#define DEFAULT_RECONNECT_MS    3000
+#define DEFAULT_NET_IP           {192, 168, 1, 100}
+#define DEFAULT_NET_MASK         {255, 255, 255, 0}
+#define DEFAULT_NET_GW           {192, 168, 1, 1}
+#define DEFAULT_NET_MAC          {0x02, 0x00, 0x00, 0x00, 0x00, 0x01}
+#define DEFAULT_UART_BAUDRATE    115200u
 
-/* AT command result codes */
 typedef enum {
     AT_OK = 0,
     AT_ERROR,
@@ -100,96 +82,30 @@ typedef enum {
     AT_NEED_REBOOT
 } at_result_t;
 
-/**
- * @brief Initialize configuration module
- * @return 0 on success, negative on error
- */
 int config_init(void);
-
-/**
- * @brief Load configuration from Flash
- * @return 0 on success, negative on error (defaults loaded)
- */
 int config_load(void);
-
-/**
- * @brief Save configuration to Flash
- * @return 0 on success, negative on error
- */
 int config_save(void);
-
-/**
- * @brief Reset configuration to factory defaults
- */
 void config_set_defaults(void);
-
-/**
- * @brief Get current configuration
- * @return Pointer to current configuration (read-only)
- */
 const device_config_t *config_get(void);
-
-/**
- * @brief Get mutable configuration for modification
- * @return Pointer to configuration structure
- */
 device_config_t *config_get_mutable(void);
-
-/**
- * @brief Process AT command received from UART1
- * @param cmd Command string (null-terminated)
- * @param response Response buffer
- * @param max_len Maximum response length
- * @return AT command result code
- */
 at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_len);
-
-/**
- * @brief Configuration task (for FreeRTOS)
- * Handles UART1 reception and AT command processing
- * @param argument Task argument (unused)
- */
-void config_task(void *argument);
-
-/**
- * @brief UART1 IDLE interrupt handler for config module
- */
-void config_uart_idle_handler(void);
-
-/**
- * @brief Start UART1 reception for configuration
- */
-void config_start_reception(void);
-
-/**
- * @brief Format IP address to string
- * @param ip IP address bytes
- * @param str Output string buffer (min 16 bytes)
- */
+void config_poll(void);
+void config_uart_rx_byte(uint8_t byte);
+bool config_try_process_frame(const uint8_t *data, uint16_t len);
+bool config_build_response_frame(const uint8_t *data,
+                                 uint16_t len,
+                                 char *response,
+                                 uint16_t max_len,
+                                 at_result_t *result);
+bool config_is_reset_requested(void);
+void config_clear_reset_requested(void);
 void config_ip_to_str(const uint8_t *ip, char *str);
-
-/**
- * @brief Parse IP address from string
- * @param str IP address string (e.g. "192.168.1.100")
- * @param ip Output IP address bytes
- * @return 0 on success, negative on error
- */
 int config_str_to_ip(const char *str, uint8_t *ip);
-
-/**
- * @brief Format MAC address to string
- * @param mac MAC address bytes
- * @param str Output string buffer (min 18 bytes)
- */
 void config_mac_to_str(const uint8_t *mac, char *str);
-
-/**
- * @brief Parse MAC address from string
- * @param str MAC address string (e.g. "00:11:22:33:44:55")
- * @param mac Output MAC address bytes
- * @return 0 on success, negative on error
- */
 int config_str_to_mac(const char *str, uint8_t *mac);
+uint8_t config_link_index_to_endpoint(uint8_t index);
+uint8_t config_uart_index_to_endpoint(uint8_t uart_index);
+bool config_endpoint_is_single(uint8_t endpoint);
 
 #ifdef __cplusplus
 }

App/flash_param.c

@@ -19,41 +19,10 @@
  * Private Variables
  *---------------------------------------------------------------------------*/
 
-/* CRC32 lookup table */
-static uint32_t g_crc_table[256];
-static bool g_crc_table_initialized = false;
-
 /*---------------------------------------------------------------------------
  * Private Functions
  *---------------------------------------------------------------------------*/
 
-/**
- * @brief Initialize CRC32 lookup table
- */
-static void crc32_init_table(void)
-{
-    uint32_t i, j, crc;
-    
-    for (i = 0; i < 256; i++)
-    {
-        crc = i;
-        for (j = 0; j < 8; j++)
-        {
-            if (crc & 1)
-            {
-                crc = (crc >> 1) ^ CRC32_POLYNOMIAL;
-            }
-            else
-            {
-                crc >>= 1;
-            }
-        }
-        g_crc_table[i] = crc;
-    }
-    
-    g_crc_table_initialized = true;
-}
-
 /**
  * @brief Unlock Flash for writing
  */
@@ -105,12 +74,6 @@ static HAL_StatusTypeDef flash_program_halfword(uint32_t addr, uint16_t data)
  */
 int flash_param_init(void)
 {
-    /* Initialize CRC table */
-    if (!g_crc_table_initialized)
-    {
-        crc32_init_table();
-    }
-    
     return 0;
 }
 
@@ -243,16 +206,22 @@ uint32_t flash_param_crc32(const void *data, uint32_t len)
     const uint8_t *p = (const uint8_t *)data;
     uint32_t crc = 0xFFFFFFFF;
     uint32_t i;
-    
-    /* Initialize table if needed */
-    if (!g_crc_table_initialized)
-    {
-        crc32_init_table();
-    }
+    uint32_t j;
 
     for (i = 0; i < len; i++)
     {
-        crc = g_crc_table[(crc ^ p[i]) & 0xFF] ^ (crc >> 8);
+        crc ^= p[i];
+        for (j = 0; j < 8u; ++j)
+        {
+            if ((crc & 1u) != 0u)
+            {
+                crc = (crc >> 1) ^ CRC32_POLYNOMIAL;
+            }
+            else
+            {
+                crc >>= 1;
+            }
+        }
     }
     
     return crc ^ 0xFFFFFFFF;

App/tcp_client.c

@@ -1,431 +1,305 @@
 /**
  * @file tcp_client.c
- * @brief TCP Client module implementation for transparent transmission with UART3
+ * @brief Indexed lwIP RAW TCP client manager.
  */
 
 #include "tcp_client.h"
-#include "config.h"
-#include "lwip/opt.h"
-#include "lwip/tcp.h"
-#include "lwip/sys.h"
-#include "lwip/sockets.h"
 
-#include "FreeRTOS.h"
-#include "task.h"
-#include "stream_buffer.h"
+#include "../Core/Inc/main.h"
+#include "../Drivers/LwIP/src/include/lwip/ip_addr.h"
+#include "../Drivers/LwIP/src/include/lwip/pbuf.h"
+#include "../Drivers/LwIP/src/include/lwip/tcp.h"
 
 #include <string.h>
 
-/*---------------------------------------------------------------------------
- * Private Variables
- *---------------------------------------------------------------------------*/
+typedef struct {
+    struct tcp_pcb *pcb;
+    uint8_t rx_ring[TCP_CLIENT_RX_BUFFER_SIZE];
+    uint16_t rx_head;
+    uint16_t rx_tail;
+    uint32_t next_retry_ms;
+    uint8_t index;
+    tcp_client_instance_config_t config;
+    tcp_client_status_t status;
+} tcp_client_ctx_t;
 
-/* Client configuration */
-static tcp_client_config_t client_config = {
-    .server_ip = {192, 168, 1, 100},
-    .server_port = TCP_CLIENT_DEFAULT_PORT,
-    .auto_reconnect = true,
-    .reconnect_interval_ms = TCP_CLIENT_RECONNECT_DELAY_MS
-};
+static tcp_client_ctx_t g_clients[TCP_CLIENT_INSTANCE_COUNT];
 
-/* Client status */
-static tcp_client_status_t client_status = {
-    .state = TCP_CLIENT_STATE_IDLE,
-    .rx_bytes = 0,
-    .tx_bytes = 0,
-    .reconnect_count = 0,
-    .errors = 0
-};
-
-/* Socket descriptor */
-static int client_socket = -1;
-
-/* Stream buffers for UART integration */
-static StreamBufferHandle_t rx_stream = NULL;  /* TCP RX -> UART TX */
-static StreamBufferHandle_t tx_stream = NULL;  /* UART RX -> TCP TX */
-
-/*---------------------------------------------------------------------------
- * Private Functions
- *---------------------------------------------------------------------------*/
-
-static int tcp_client_send_all(int sock, const uint8_t *data, uint16_t len)
+static uint16_t ring_free(uint16_t head, uint16_t tail, uint16_t size)
 {
-    uint16_t total = 0;
+    return (head >= tail) ? (uint16_t)(size - head + tail - 1u) : (uint16_t)(tail - head - 1u);
+}
 
-    while (total < len)
-    {
-        int sent = send(sock, data + total, len - total, 0);
-        if (sent > 0)
-        {
-            total += (uint16_t)sent;
+static err_t tcp_client_on_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+    tcp_client_ctx_t *ctx = (tcp_client_ctx_t *)arg;
+    struct pbuf *q;
+
+    if (ctx == NULL) {
+        if (p != NULL) {
+            pbuf_free(p);
         }
-        else
-        {
-            return -1;
+        return ERR_ARG;
+    }
+    if (err != ERR_OK) {
+        if (p != NULL) {
+            pbuf_free(p);
+        }
+        return err;
+    }
+    if (p == NULL) {
+        tcp_arg(pcb, NULL);
+        tcp_recv(pcb, NULL);
+        tcp_sent(pcb, NULL);
+        tcp_err(pcb, NULL);
+        tcp_abort(pcb);
+        ctx->pcb = NULL;
+        ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
+        ctx->next_retry_ms = HAL_GetTick() + ctx->config.reconnect_interval_ms;
+        return ERR_ABRT;
+    }
+
+    for (q = p; q != NULL; q = q->next) {
+        const uint8_t *src = (const uint8_t *)q->payload;
+        for (uint16_t i = 0; i < q->len; ++i) {
+            if (ring_free(ctx->rx_head, ctx->rx_tail, TCP_CLIENT_RX_BUFFER_SIZE) == 0u) {
+                ctx->status.errors++;
+                break;
+            }
+            ctx->rx_ring[ctx->rx_head] = src[i];
+            ctx->rx_head = (uint16_t)((ctx->rx_head + 1u) % TCP_CLIENT_RX_BUFFER_SIZE);
+            ctx->status.rx_bytes++;
         }
     }
 
-    return (int)total;
+    tcp_recved(pcb, p->tot_len);
+    pbuf_free(p);
+    return ERR_OK;
 }
 
-/**
- * @brief Internal connect function
- */
-static int tcp_client_do_connect(void)
+static err_t tcp_client_on_sent(void *arg, struct tcp_pcb *pcb, u16_t len)
 {
-    struct sockaddr_in server_addr;
-    int ret;
+    tcp_client_ctx_t *ctx = (tcp_client_ctx_t *)arg;
+    (void)pcb;
+    if (ctx != NULL) {
+        ctx->status.tx_bytes += len;
+    }
+    return ERR_OK;
+}
 
-    if (client_socket >= 0)
-    {
-        /* Already connected */
+static void tcp_client_on_err(void *arg, err_t err)
+{
+    tcp_client_ctx_t *ctx = (tcp_client_ctx_t *)arg;
+    if (ctx == NULL) {
+        return;
+    }
+    ctx->pcb = NULL;
+    ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
+    ctx->status.errors++;
+    ctx->next_retry_ms = HAL_GetTick() + ctx->config.reconnect_interval_ms;
+    (void)err;
+}
+
+static err_t tcp_client_on_connected(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+    tcp_client_ctx_t *ctx = (tcp_client_ctx_t *)arg;
+
+    if (ctx == NULL) {
+        return ERR_ARG;
+    }
+    if (err != ERR_OK) {
+        ctx->pcb = NULL;
+        ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
+        ctx->status.errors++;
+        ctx->next_retry_ms = HAL_GetTick() + ctx->config.reconnect_interval_ms;
+        return err;
+    }
+
+    ctx->pcb = pcb;
+    ctx->status.state = TCP_CLIENT_STATE_CONNECTED;
+    tcp_nagle_disable(pcb);
+    tcp_arg(pcb, ctx);
+    tcp_recv(pcb, tcp_client_on_recv);
+    tcp_sent(pcb, tcp_client_on_sent);
+    tcp_err(pcb, tcp_client_on_err);
+    return ERR_OK;
+}
+
+int tcp_client_init_all(void)
+{
+    memset(g_clients, 0, sizeof(g_clients));
+    for (uint8_t i = 0; i < TCP_CLIENT_INSTANCE_COUNT; ++i) {
+        g_clients[i].index = i;
+        g_clients[i].status.state = TCP_CLIENT_STATE_IDLE;
+        g_clients[i].config.reconnect_interval_ms = TCP_CLIENT_RECONNECT_DELAY_MS;
+        g_clients[i].config.auto_reconnect = true;
+    }
+    return 0;
+}
+
+int tcp_client_config(uint8_t instance, const tcp_client_instance_config_t *config)
+{
+    if (instance >= TCP_CLIENT_INSTANCE_COUNT || config == NULL) {
+        return -1;
+    }
+    g_clients[instance].config = *config;
+    return 0;
+}
+
+int tcp_client_connect(uint8_t instance)
+{
+    struct tcp_pcb *pcb;
+    ip_addr_t remote_addr;
+    err_t err;
+    tcp_client_ctx_t *ctx;
+
+    if (instance >= TCP_CLIENT_INSTANCE_COUNT) {
+        return -1;
+    }
+    ctx = &g_clients[instance];
+    if (!ctx->config.enabled) {
+        return 0;
+    }
+    if (ctx->pcb != NULL) {
         return 0;
     }
 
-    client_status.state = TCP_CLIENT_STATE_CONNECTING;
-    
-    /* Create socket */
-    client_socket = socket(AF_INET, SOCK_STREAM, 0);
-    if (client_socket < 0)
-    {
-        client_status.state = TCP_CLIENT_STATE_ERROR;
-        client_status.errors++;
+    pcb = tcp_new_ip_type(IPADDR_TYPE_V4);
+    if (pcb == NULL) {
+        ctx->status.errors++;
+        ctx->status.state = TCP_CLIENT_STATE_ERROR;
         return -1;
     }
-    
-    /* Prepare server address */
-    memset(&server_addr, 0, sizeof(server_addr));
-    server_addr.sin_family = AF_INET;
-    server_addr.sin_port = htons(client_config.server_port);
-    server_addr.sin_addr.s_addr = ((uint32_t)client_config.server_ip[0]) |
-                                  ((uint32_t)client_config.server_ip[1] << 8) |
-                                  ((uint32_t)client_config.server_ip[2] << 16) |
-                                  ((uint32_t)client_config.server_ip[3] << 24);
-    
-    /* Connect to server */
-    ret = connect(client_socket, (struct sockaddr *)&server_addr, sizeof(server_addr));
-    if (ret < 0)
-    {
-        close(client_socket);
-        client_socket = -1;
-        client_status.state = TCP_CLIENT_STATE_DISCONNECTED;
-        client_status.errors++;
-        return -1;
-    }
-    
-    client_status.state = TCP_CLIENT_STATE_CONNECTED;
-    
-    return 0;
-}
-
-/*---------------------------------------------------------------------------
- * Public Functions
- *---------------------------------------------------------------------------*/
-
-/**
- * @brief Initialize TCP Client module
- */
-int tcp_client_init(const tcp_client_config_t *config)
-{
-    if (config != NULL)
-    {
-        memcpy(&client_config, config, sizeof(tcp_client_config_t));
-    }
-    
-    /* Create stream buffers */
-    if (rx_stream == NULL)
-    {
-        rx_stream = xStreamBufferCreate(TCP_CLIENT_RX_BUFFER_SIZE, 1);
-        if (rx_stream == NULL)
-        {
+    if (ctx->config.local_port != 0u) {
+        err = tcp_bind(pcb, IP_ANY_TYPE, ctx->config.local_port);
+        if (err != ERR_OK) {
+            tcp_abort(pcb);
+            ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
+            ctx->status.errors++;
+            ctx->next_retry_ms = HAL_GetTick() + ctx->config.reconnect_interval_ms;
             return -1;
         }
     }
 
-    if (tx_stream == NULL)
-    {
-        tx_stream = xStreamBufferCreate(TCP_CLIENT_TX_BUFFER_SIZE, 1);
-        if (tx_stream == NULL)
-        {
-            return -1;
-        }
-    }
+    IP_ADDR4(&remote_addr,
+             ctx->config.remote_ip[0],
+             ctx->config.remote_ip[1],
+             ctx->config.remote_ip[2],
+             ctx->config.remote_ip[3]);
 
-    client_status.state = TCP_CLIENT_STATE_IDLE;
-    
-    return 0;
-}
-
-/**
- * @brief Connect to remote server
- */
-int tcp_client_connect(void)
-{
-    return tcp_client_do_connect();
-}
-
-/**
- * @brief Disconnect from server
- */
-int tcp_client_disconnect(void)
-{
-    if (client_socket >= 0)
-    {
-        close(client_socket);
-        client_socket = -1;
-    }
-    
-    client_status.state = TCP_CLIENT_STATE_DISCONNECTED;
-    
-    return 0;
-}
-
-/**
- * @brief Send data to server
- */
-int tcp_client_send(const uint8_t *data, uint16_t len)
-{
-    int sent;
-    
-    if (client_socket < 0)
-    {
+    ctx->status.state = TCP_CLIENT_STATE_CONNECTING;
+    tcp_arg(pcb, ctx);
+    tcp_err(pcb, tcp_client_on_err);
+    err = tcp_connect(pcb, &remote_addr, ctx->config.remote_port, tcp_client_on_connected);
+    if (err != ERR_OK) {
+        tcp_err(pcb, NULL);
+        tcp_abort(pcb);
+        ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
+        ctx->status.errors++;
+        ctx->next_retry_ms = HAL_GetTick() + ctx->config.reconnect_interval_ms;
         return -1;
     }
 
-    sent = tcp_client_send_all(client_socket, data, len);
-    if (sent > 0)
-    {
-        client_status.tx_bytes += sent;
-    }
-    else if (sent < 0)
-    {
-        /* Connection error */
-        close(client_socket);
-        client_socket = -1;
-        client_status.state = TCP_CLIENT_STATE_DISCONNECTED;
-        client_status.errors++;
-    }
-    
-    return sent;
-}
-
-/**
- * @brief Receive data from server
- */
-int tcp_client_recv(uint8_t *data, uint16_t max_len, uint32_t timeout_ms)
-{
-    int received;
-    struct timeval tv;
-    
-    if (client_socket < 0)
-    {
-        return -1;
-    }
-    
-    /* Set receive timeout */
-    tv.tv_sec = timeout_ms / 1000;
-    tv.tv_usec = (timeout_ms % 1000) * 1000;
-    setsockopt(client_socket, SOL_SOCKET, SO_RCVTIMEO, &tv, sizeof(tv));
-    
-    received = recv(client_socket, data, max_len, 0);
-    if (received > 0)
-    {
-        client_status.rx_bytes += received;
-    }
-    else if (received == 0)
-    {
-        /* Connection closed by server */
-        close(client_socket);
-        client_socket = -1;
-        client_status.state = TCP_CLIENT_STATE_DISCONNECTED;
-    }
-    
-    return received;
-}
-
-/**
- * @brief Check if connected to server
- */
-bool tcp_client_is_connected(void)
-{
-    return (client_socket >= 0);
-}
-
-/**
- * @brief Update server configuration
- */
-int tcp_client_set_server(const uint8_t *ip, uint16_t port)
-{
-    if (ip == NULL)
-    {
-        return -1;
-    }
-    
-    /* Disconnect if connected */
-    if (client_socket >= 0)
-    {
-        tcp_client_disconnect();
-    }
-    
-    memcpy(client_config.server_ip, ip, 4);
-    client_config.server_port = port;
-    
+    ctx->pcb = pcb;
     return 0;
 }
 
-/**
- * @brief Get TCP Client status
- */
-void tcp_client_get_status(tcp_client_status_t *status)
+int tcp_client_disconnect(uint8_t instance)
 {
-    if (status != NULL)
-    {
-        memcpy(status, &client_status, sizeof(tcp_client_status_t));
+    tcp_client_ctx_t *ctx;
+
+    if (instance >= TCP_CLIENT_INSTANCE_COUNT) {
+        return -1;
+    }
+    ctx = &g_clients[instance];
+    if (ctx->pcb != NULL) {
+        tcp_arg(ctx->pcb, NULL);
+        tcp_recv(ctx->pcb, NULL);
+        tcp_sent(ctx->pcb, NULL);
+        tcp_err(ctx->pcb, NULL);
+        tcp_abort(ctx->pcb);
+        ctx->pcb = NULL;
+    }
+    ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
+    ctx->rx_head = 0u;
+    ctx->rx_tail = 0u;
+    return 0;
+}
+
+int tcp_client_send(uint8_t instance, const uint8_t *data, uint16_t len)
+{
+    err_t err;
+    tcp_client_ctx_t *ctx;
+
+    if (instance >= TCP_CLIENT_INSTANCE_COUNT || data == NULL || len == 0u) {
+        return -1;
+    }
+    ctx = &g_clients[instance];
+    if (ctx->pcb == NULL) {
+        return -1;
+    }
+    if (tcp_sndbuf(ctx->pcb) < len) {
+        return 0;
+    }
+    err = tcp_write(ctx->pcb, data, len, TCP_WRITE_FLAG_COPY);
+    if (err != ERR_OK) {
+        ctx->status.errors++;
+        return -1;
+    }
+    err = tcp_output(ctx->pcb);
+    if (err != ERR_OK) {
+        ctx->status.errors++;
+        return -1;
+    }
+    return (int)len;
+}
+
+int tcp_client_recv(uint8_t instance, uint8_t *data, uint16_t max_len)
+{
+    uint16_t copied = 0u;
+    tcp_client_ctx_t *ctx;
+
+    if (instance >= TCP_CLIENT_INSTANCE_COUNT || data == NULL || max_len == 0u) {
+        return -1;
+    }
+    ctx = &g_clients[instance];
+    while (copied < max_len && ctx->rx_tail != ctx->rx_head) {
+        data[copied++] = ctx->rx_ring[ctx->rx_tail];
+        ctx->rx_tail = (uint16_t)((ctx->rx_tail + 1u) % TCP_CLIENT_RX_BUFFER_SIZE);
+    }
+    return (int)copied;
+}
+
+bool tcp_client_is_connected(uint8_t instance)
+{
+    return (instance < TCP_CLIENT_INSTANCE_COUNT) &&
+           (g_clients[instance].pcb != NULL) &&
+           (g_clients[instance].status.state == TCP_CLIENT_STATE_CONNECTED);
+}
+
+void tcp_client_get_status(uint8_t instance, tcp_client_status_t *status)
+{
+    if (instance < TCP_CLIENT_INSTANCE_COUNT && status != NULL) {
+        *status = g_clients[instance].status;
     }
 }
 
-/**
- * @brief Get RX StreamBuffer handle
- */
-void *tcp_client_get_rx_stream(void)
+void tcp_client_poll(void)
 {
-    return rx_stream;
-}
+    uint32_t now = HAL_GetTick();
 
-/**
- * @brief Get TX StreamBuffer handle
- */
-void *tcp_client_get_tx_stream(void)
-{
-    return tx_stream;
-}
-
-/**
- * @brief TCP Client task
- */
-void tcp_client_task(void *argument)
-{
-    const device_config_t *cfg;
-    tcp_client_config_t task_cfg;
-    uint8_t rx_buffer[256];
-    uint8_t tx_buffer[256];
-    int received;
-    size_t tx_len;
-    fd_set read_fds;
-    struct timeval tv;
-    uint32_t reconnect_timer = 0;
-    
-    (void)argument;
-    
-    /* Initialize client */
-    task_cfg.server_ip[0] = 192;
-    task_cfg.server_ip[1] = 168;
-    task_cfg.server_ip[2] = 1;
-    task_cfg.server_ip[3] = 100;
-    task_cfg.server_port = TCP_CLIENT_DEFAULT_PORT;
-    task_cfg.auto_reconnect = true;
-    task_cfg.reconnect_interval_ms = TCP_CLIENT_RECONNECT_DELAY_MS;
-
-    cfg = config_get();
-    if (cfg != NULL)
-    {
-        memcpy(task_cfg.server_ip, cfg->remote_ip, sizeof(task_cfg.server_ip));
-        if (cfg->remote_port > 0)
-        {
-            task_cfg.server_port = cfg->remote_port;
-        }
-        if (cfg->reconnect_interval > 0)
-        {
-            task_cfg.reconnect_interval_ms = cfg->reconnect_interval;
-        }
-    }
-
-    tcp_client_init(&task_cfg);
-    
-    while (1)
-    {
-        /* Handle connection state */
-        if (client_socket < 0)
-        {
-            /* Not connected - try to reconnect */
-            if (client_config.auto_reconnect)
-            {
-                if (xTaskGetTickCount() - reconnect_timer >= pdMS_TO_TICKS(client_config.reconnect_interval_ms))
-                {
-                    if (tcp_client_do_connect() == 0)
-                    {
-                        /* Connected successfully */
-                        client_status.reconnect_count++;
-                    }
-                    reconnect_timer = xTaskGetTickCount();
-                }
-            }
-            
-            /* Wait before retry */
-            vTaskDelay(pdMS_TO_TICKS(100));
+    for (uint8_t i = 0; i < TCP_CLIENT_INSTANCE_COUNT; ++i) {
+        tcp_client_ctx_t *ctx = &g_clients[i];
+        if (!ctx->config.enabled || !ctx->config.auto_reconnect || tcp_client_is_connected(i)) {
             continue;
         }
-        
-        /* Handle data transfer if connected */
-        
-        /* Check for data from TCP server */
-        FD_ZERO(&read_fds);
-        FD_SET(client_socket, &read_fds);
-        tv.tv_sec = 0;
-        tv.tv_usec = 10000;  /* 10ms timeout */
-        
-        if (select(client_socket + 1, &read_fds, NULL, NULL, &tv) > 0)
-        {
-            if (FD_ISSET(client_socket, &read_fds))
-            {
-                received = recv(client_socket, rx_buffer, sizeof(rx_buffer), 0);
-                if (received > 0)
-                {
-                    /* Forward to UART via stream buffer */
-                    xStreamBufferSend(rx_stream, rx_buffer, received, pdMS_TO_TICKS(10));
-                    client_status.rx_bytes += received;
-                }
-                else if (received == 0)
-                {
-                    /* Connection closed */
-                    close(client_socket);
-                    client_socket = -1;
-                    client_status.state = TCP_CLIENT_STATE_DISCONNECTED;
-                    reconnect_timer = xTaskGetTickCount();
-                }
-                else
-                {
-                    /* Error */
-                    close(client_socket);
-                    client_socket = -1;
-                    client_status.state = TCP_CLIENT_STATE_DISCONNECTED;
-                    client_status.errors++;
-                    reconnect_timer = xTaskGetTickCount();
-                }
-            }
+        if ((ctx->pcb != NULL) && (ctx->status.state == TCP_CLIENT_STATE_CONNECTING)) {
+            continue;
         }
-        
-        /* Check for data from UART to send to TCP */
-        tx_len = xStreamBufferReceive(tx_stream, tx_buffer, sizeof(tx_buffer), 0);
-        if (tx_len > 0)
-        {
-            int sent = tcp_client_send_all(client_socket, tx_buffer, (uint16_t)tx_len);
-            if (sent > 0)
-            {
-                client_status.tx_bytes += sent;
-            }
-            else if (sent < 0)
-            {
-                /* Send error */
-                close(client_socket);
-                client_socket = -1;
-                client_status.state = TCP_CLIENT_STATE_DISCONNECTED;
-                client_status.errors++;
-                reconnect_timer = xTaskGetTickCount();
-            }
+        if (now >= ctx->next_retry_ms) {
+            ctx->status.reconnect_count++;
+            ctx->next_retry_ms = now + ctx->config.reconnect_interval_ms;
+            (void)tcp_client_connect(i);
         }
-        
-        /* Small delay to prevent tight loop */
-        vTaskDelay(pdMS_TO_TICKS(1));
     }
 }

App/tcp_client.h

@@ -1,48 +1,39 @@
 /**
  * @file tcp_client.h
- * @brief TCP Client module for transparent transmission with UART3
+ * @brief Indexed lwIP RAW TCP client manager.
  */
 
 #ifndef __TCP_CLIENT_H__
 #define __TCP_CLIENT_H__
 
-#include <stdint.h>
 #include <stdbool.h>
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/* Default TCP Client settings */
-#define TCP_CLIENT_DEFAULT_PORT     8081
-#define TCP_CLIENT_DEFAULT_SERVER   "192.168.1.100"
+#define TCP_CLIENT_INSTANCE_COUNT      2u
+#define TCP_CLIENT_RX_BUFFER_SIZE      512u
+#define TCP_CLIENT_RECONNECT_DELAY_MS  3000u
 
-/* Reconnect settings */
-#define TCP_CLIENT_RECONNECT_DELAY_MS   3000
-#define TCP_CLIENT_MAX_RECONNECT_TRIES  0   /* 0 = infinite */
-
-/* Buffer sizes */
-#define TCP_CLIENT_RX_BUFFER_SIZE   512
-#define TCP_CLIENT_TX_BUFFER_SIZE   512
-
-/* TCP Client state */
 typedef enum {
-    TCP_CLIENT_STATE_IDLE,
+    TCP_CLIENT_STATE_IDLE = 0,
     TCP_CLIENT_STATE_CONNECTING,
     TCP_CLIENT_STATE_CONNECTED,
     TCP_CLIENT_STATE_DISCONNECTED,
     TCP_CLIENT_STATE_ERROR
 } tcp_client_state_t;
 
-/* TCP Client configuration */
 typedef struct {
-    uint8_t server_ip[4];       /* Server IP address */
-    uint16_t server_port;       /* Server port */
-    bool auto_reconnect;        /* Auto reconnect on disconnect */
-    uint16_t reconnect_interval_ms; /* Reconnect interval */
-} tcp_client_config_t;
+    uint8_t remote_ip[4];
+    uint16_t local_port;
+    uint16_t remote_port;
+    uint16_t reconnect_interval_ms;
+    bool enabled;
+    bool auto_reconnect;
+} tcp_client_instance_config_t;
 
-/* TCP Client status */
 typedef struct {
     tcp_client_state_t state;
     uint32_t rx_bytes;
@@ -51,79 +42,15 @@ typedef struct {
     uint32_t errors;
 } tcp_client_status_t;
 
-/**
- * @brief Initialize TCP Client module
- * @param config Client configuration
- * @return 0 on success, negative on error
- */
-int tcp_client_init(const tcp_client_config_t *config);
-
-/**
- * @brief Connect to remote server
- * @return 0 on success, negative on error
- */
-int tcp_client_connect(void);
-
-/**
- * @brief Disconnect from server
- * @return 0 on success, negative on error
- */
-int tcp_client_disconnect(void);
-
-/**
- * @brief Send data to server
- * @param data Data buffer
- * @param len Data length
- * @return Number of bytes sent, negative on error
- */
-int tcp_client_send(const uint8_t *data, uint16_t len);
-
-/**
- * @brief Receive data from server
- * @param data Data buffer
- * @param max_len Maximum length to receive
- * @param timeout_ms Timeout in milliseconds (0 = non-blocking)
- * @return Number of bytes received, 0 if no data, negative on error
- */
-int tcp_client_recv(uint8_t *data, uint16_t max_len, uint32_t timeout_ms);
-
-/**
- * @brief Check if connected to server
- * @return true if connected
- */
-bool tcp_client_is_connected(void);
-
-/**
- * @brief Update server configuration (for AT command)
- * @param ip Server IP address (4 bytes)
- * @param port Server port
- * @return 0 on success, negative on error
- */
-int tcp_client_set_server(const uint8_t *ip, uint16_t port);
-
-/**
- * @brief Get TCP Client status
- * @param status Pointer to status structure
- */
-void tcp_client_get_status(tcp_client_status_t *status);
-
-/**
- * @brief Get TCP Client RX StreamBuffer handle for UART integration
- * @return StreamBuffer handle for receiving data from TCP
- */
-void *tcp_client_get_rx_stream(void);
-
-/**
- * @brief Get TCP Client TX StreamBuffer handle for UART integration
- * @return StreamBuffer handle for sending data to TCP
- */
-void *tcp_client_get_tx_stream(void);
-
-/**
- * @brief TCP Client task function (for FreeRTOS)
- * @param argument Task argument (unused)
- */
-void tcp_client_task(void *argument);
+int tcp_client_init_all(void);
+int tcp_client_config(uint8_t instance, const tcp_client_instance_config_t *config);
+int tcp_client_connect(uint8_t instance);
+int tcp_client_disconnect(uint8_t instance);
+int tcp_client_send(uint8_t instance, const uint8_t *data, uint16_t len);
+int tcp_client_recv(uint8_t instance, uint8_t *data, uint16_t max_len);
+bool tcp_client_is_connected(uint8_t instance);
+void tcp_client_get_status(uint8_t instance, tcp_client_status_t *status);
+void tcp_client_poll(void);
 
 #ifdef __cplusplus
 }

App/tcp_server.c

@@ -1,405 +1,273 @@
 /**
  * @file tcp_server.c
- * @brief TCP Server module implementation for transparent transmission with UART2
+ * @brief Indexed lwIP RAW TCP server manager.
  */
 
 #include "tcp_server.h"
-#include "config.h"
-#include "lwip/opt.h"
-#include "lwip/tcp.h"
-#include "lwip/sys.h"
-#include "lwip/sockets.h"
 
-#include "FreeRTOS.h"
-#include "task.h"
-#include "stream_buffer.h"
+#include "../Drivers/LwIP/src/include/lwip/pbuf.h"
+#include "../Drivers/LwIP/src/include/lwip/tcp.h"
+
+#include "SEGGER_RTT.h"
 
 #include <string.h>
 
-/*---------------------------------------------------------------------------
- * Private Variables
- *---------------------------------------------------------------------------*/
+typedef struct {
+    struct tcp_pcb *listen_pcb;
+    struct tcp_pcb *client_pcb;
+    uint8_t rx_ring[TCP_SERVER_RX_BUFFER_SIZE];
+    uint16_t rx_head;
+    uint16_t rx_tail;
+    uint8_t index;
+    tcp_server_instance_config_t config;
+    tcp_server_status_t status;
+} tcp_server_ctx_t;
 
-/* Server configuration */
-static tcp_server_config_t server_config = {
-    .port = TCP_SERVER_DEFAULT_PORT,
-    .auto_reconnect = true
-};
+static tcp_server_ctx_t g_servers[TCP_SERVER_INSTANCE_COUNT];
 
-/* Server status */
-static tcp_server_status_t server_status = {
-    .state = TCP_SERVER_STATE_IDLE,
-    .rx_bytes = 0,
-    .tx_bytes = 0,
-    .connections = 0,
-    .errors = 0
-};
-
-/* Socket descriptors */
-static int listen_socket = -1;
-static int client_socket = -1;
-
-/* Stream buffers for UART integration */
-static StreamBufferHandle_t rx_stream = NULL;  /* TCP RX -> UART TX */
-static StreamBufferHandle_t tx_stream = NULL;  /* UART RX -> TCP TX */
-
-/*---------------------------------------------------------------------------
- * Public Functions
- *---------------------------------------------------------------------------*/
-
-static int tcp_server_send_all(int sock, const uint8_t *data, uint16_t len)
+static uint16_t ring_free(uint16_t head, uint16_t tail, uint16_t size)
 {
-    uint16_t total = 0;
-
-    while (total < len)
-    {
-        int sent = send(sock, data + total, len - total, 0);
-        if (sent > 0)
-        {
-            total += (uint16_t)sent;
-        }
-        else
-        {
-            return -1;
-        }
-    }
-
-    return (int)total;
+    return (head >= tail) ? (uint16_t)(size - head + tail - 1u) : (uint16_t)(tail - head - 1u);
 }
 
-/**
- * @brief Initialize TCP Server module
- */
-int tcp_server_init(const tcp_server_config_t *config)
+static err_t tcp_server_on_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
 {
-    if (config != NULL)
-    {
-        memcpy(&server_config, config, sizeof(tcp_server_config_t));
+    tcp_server_ctx_t *ctx = (tcp_server_ctx_t *)arg;
+    struct pbuf *q;
+
+    if (ctx == NULL) {
+        if (p != NULL) {
+            pbuf_free(p);
+        }
+        return ERR_ARG;
+    }
+    if (err != ERR_OK) {
+        if (p != NULL) {
+            pbuf_free(p);
+        }
+        return err;
+    }
+    if (p == NULL) {
+        tcp_arg(pcb, NULL);
+        tcp_recv(pcb, NULL);
+        tcp_sent(pcb, NULL);
+        tcp_err(pcb, NULL);
+        tcp_abort(pcb);
+        ctx->client_pcb = NULL;
+        ctx->status.state = ctx->config.enabled ? TCP_SERVER_STATE_LISTENING : TCP_SERVER_STATE_IDLE;
+        return ERR_ABRT;
     }
 
-    /* Create stream buffers */
-    if (rx_stream == NULL)
-    {
-        rx_stream = xStreamBufferCreate(TCP_SERVER_RX_BUFFER_SIZE, 1);
-        if (rx_stream == NULL)
-        {
-            return -1;
+    for (q = p; q != NULL; q = q->next) {
+        const uint8_t *src = (const uint8_t *)q->payload;
+        for (uint16_t i = 0; i < q->len; ++i) {
+            if (ring_free(ctx->rx_head, ctx->rx_tail, TCP_SERVER_RX_BUFFER_SIZE) == 0u) {
+                ctx->status.errors++;
+                break;
+            }
+            ctx->rx_ring[ctx->rx_head] = src[i];
+            ctx->rx_head = (uint16_t)((ctx->rx_head + 1u) % TCP_SERVER_RX_BUFFER_SIZE);
+            ctx->status.rx_bytes++;
         }
     }
 
-    if (tx_stream == NULL)
-    {
-        tx_stream = xStreamBufferCreate(TCP_SERVER_TX_BUFFER_SIZE, 1);
-        if (tx_stream == NULL)
-        {
-            return -1;
-        }
+    tcp_recved(pcb, p->tot_len);
+    pbuf_free(p);
+    return ERR_OK;
+}
+
+static err_t tcp_server_on_sent(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+    tcp_server_ctx_t *ctx = (tcp_server_ctx_t *)arg;
+    (void)pcb;
+    if (ctx != NULL) {
+        ctx->status.tx_bytes += len;
+    }
+    return ERR_OK;
+}
+
+static void tcp_server_on_err(void *arg, err_t err)
+{
+    tcp_server_ctx_t *ctx = (tcp_server_ctx_t *)arg;
+    if (ctx == NULL) {
+        return;
+    }
+    ctx->client_pcb = NULL;
+    ctx->status.state = ctx->config.enabled ? TCP_SERVER_STATE_LISTENING : TCP_SERVER_STATE_IDLE;
+    ctx->status.errors++;
+    SEGGER_RTT_printf(0, "TCP server[%u] connection error=%d\r\n", ctx->index, (int)err);
+}
+
+static err_t tcp_server_on_accept(void *arg, struct tcp_pcb *newpcb, err_t err)
+{
+    tcp_server_ctx_t *ctx = (tcp_server_ctx_t *)arg;
+
+    if (ctx == NULL || err != ERR_OK) {
+        return (ctx == NULL) ? ERR_ARG : err;
+    }
+    if (ctx->client_pcb != NULL) {
+        tcp_abort(newpcb);
+        return ERR_ABRT;
     }
 
-    server_status.state = TCP_SERVER_STATE_IDLE;
+    ctx->client_pcb = newpcb;
+    ctx->status.state = TCP_SERVER_STATE_CONNECTED;
+    ctx->status.connections++;
+    tcp_nagle_disable(newpcb);
+    tcp_arg(newpcb, ctx);
+    tcp_recv(newpcb, tcp_server_on_recv);
+    tcp_sent(newpcb, tcp_server_on_sent);
+    tcp_err(newpcb, tcp_server_on_err);
+    return ERR_OK;
+}
 
+int tcp_server_init_all(void)
+{
+    memset(g_servers, 0, sizeof(g_servers));
+    for (uint8_t i = 0; i < TCP_SERVER_INSTANCE_COUNT; ++i) {
+        g_servers[i].index = i;
+        g_servers[i].status.state = TCP_SERVER_STATE_IDLE;
+    }
     return 0;
 }
 
-/**
- * @brief Start TCP Server
- */
-int tcp_server_start(void)
+int tcp_server_config(uint8_t instance, const tcp_server_instance_config_t *config)
 {
-    struct sockaddr_in server_addr;
-    int opt = 1;
+    if (instance >= TCP_SERVER_INSTANCE_COUNT || config == NULL) {
+        return -1;
+    }
+    g_servers[instance].config = *config;
+    return 0;
+}
 
-    if (listen_socket >= 0)
-    {
-        /* Already started */
+int tcp_server_start(uint8_t instance)
+{
+    struct tcp_pcb *pcb;
+    err_t err;
+    tcp_server_ctx_t *ctx;
+
+    if (instance >= TCP_SERVER_INSTANCE_COUNT) {
+        return -1;
+    }
+    ctx = &g_servers[instance];
+    if (!ctx->config.enabled) {
+        ctx->status.state = TCP_SERVER_STATE_IDLE;
+        return 0;
+    }
+    if (ctx->listen_pcb != NULL) {
         return 0;
     }
 
-    /* Create socket */
-    listen_socket = socket(AF_INET, SOCK_STREAM, 0);
-    if (listen_socket < 0)
-    {
-        server_status.state = TCP_SERVER_STATE_ERROR;
-        server_status.errors++;
+    pcb = tcp_new_ip_type(IPADDR_TYPE_V4);
+    if (pcb == NULL) {
+        ctx->status.errors++;
         return -1;
     }
 
-    /* Set socket options */
-    setsockopt(listen_socket, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(opt));
-    
-    /* Bind to port */
-    memset(&server_addr, 0, sizeof(server_addr));
-    server_addr.sin_family = AF_INET;
-    server_addr.sin_addr.s_addr = INADDR_ANY;
-    server_addr.sin_port = htons(server_config.port);
-    
-    if (bind(listen_socket, (struct sockaddr *)&server_addr, sizeof(server_addr)) < 0)
-    {
-        close(listen_socket);
-        listen_socket = -1;
-        server_status.state = TCP_SERVER_STATE_ERROR;
-        server_status.errors++;
+    err = tcp_bind(pcb, IP_ANY_TYPE, ctx->config.port);
+    if (err != ERR_OK) {
+        tcp_abort(pcb);
+        ctx->status.errors++;
         return -1;
     }
 
-    /* Start listening */
-    if (listen(listen_socket, TCP_SERVER_MAX_CONNECTIONS) < 0)
-    {
-        close(listen_socket);
-        listen_socket = -1;
-        server_status.state = TCP_SERVER_STATE_ERROR;
-        server_status.errors++;
+    ctx->listen_pcb = tcp_listen_with_backlog(pcb, 1);
+    if (ctx->listen_pcb == NULL) {
+        ctx->status.errors++;
         return -1;
     }
 
-    server_status.state = TCP_SERVER_STATE_LISTENING;
-    
+    tcp_arg(ctx->listen_pcb, ctx);
+    tcp_accept(ctx->listen_pcb, tcp_server_on_accept);
+    ctx->status.state = TCP_SERVER_STATE_LISTENING;
     return 0;
 }
 
-/**
- * @brief Stop TCP Server
- */
-int tcp_server_stop(void)
+int tcp_server_stop(uint8_t instance)
 {
-    if (client_socket >= 0)
-    {
-        close(client_socket);
-        client_socket = -1;
+    tcp_server_ctx_t *ctx;
+
+    if (instance >= TCP_SERVER_INSTANCE_COUNT) {
+        return -1;
+    }
+    ctx = &g_servers[instance];
+
+    if (ctx->client_pcb != NULL) {
+        tcp_arg(ctx->client_pcb, NULL);
+        tcp_recv(ctx->client_pcb, NULL);
+        tcp_sent(ctx->client_pcb, NULL);
+        tcp_err(ctx->client_pcb, NULL);
+        tcp_abort(ctx->client_pcb);
+        ctx->client_pcb = NULL;
+    }
+    if (ctx->listen_pcb != NULL) {
+        tcp_arg(ctx->listen_pcb, NULL);
+        tcp_accept(ctx->listen_pcb, NULL);
+        if (tcp_close(ctx->listen_pcb) != ERR_OK) {
+            tcp_abort(ctx->listen_pcb);
+        }
+        ctx->listen_pcb = NULL;
     }
 
-    if (listen_socket >= 0)
-    {
-        close(listen_socket);
-        listen_socket = -1;
-    }
-    
-    server_status.state = TCP_SERVER_STATE_IDLE;
-    
+    ctx->status.state = TCP_SERVER_STATE_IDLE;
+    ctx->rx_head = 0u;
+    ctx->rx_tail = 0u;
     return 0;
 }
 
-/**
- * @brief Send data to connected client
- */
-int tcp_server_send(const uint8_t *data, uint16_t len)
+int tcp_server_send(uint8_t instance, const uint8_t *data, uint16_t len)
 {
-    int sent;
+    err_t err;
+    tcp_server_ctx_t *ctx;
 
-    if (client_socket < 0)
-    {
+    if (instance >= TCP_SERVER_INSTANCE_COUNT || data == NULL || len == 0u) {
         return -1;
     }
-    
-    sent = tcp_server_send_all(client_socket, data, len);
-    if (sent > 0)
-    {
-        server_status.tx_bytes += sent;
-    }
-    else if (sent < 0)
-    {
-        /* Connection error */
-        close(client_socket);
-        client_socket = -1;
-        server_status.state = TCP_SERVER_STATE_LISTENING;
-        server_status.errors++;
-    }
-    
-    return sent;
-}
-
-/**
- * @brief Receive data from connected client
- */
-int tcp_server_recv(uint8_t *data, uint16_t max_len, uint32_t timeout_ms)
-{
-    int received;
-    struct timeval tv;
-    
-    if (client_socket < 0)
-    {
+    ctx = &g_servers[instance];
+    if (ctx->client_pcb == NULL) {
         return -1;
     }
-    
-    /* Set receive timeout */
-    tv.tv_sec = timeout_ms / 1000;
-    tv.tv_usec = (timeout_ms % 1000) * 1000;
-    setsockopt(client_socket, SOL_SOCKET, SO_RCVTIMEO, &tv, sizeof(tv));
-    
-    received = recv(client_socket, data, max_len, 0);
-    if (received > 0)
-    {
-        server_status.rx_bytes += received;
-    }
-    else if (received == 0)
-    {
-        /* Connection closed by client */
-        close(client_socket);
-        client_socket = -1;
-        server_status.state = TCP_SERVER_STATE_LISTENING;
-    }
-    else if (received < 0)
-    {
-        /* Timeout or error - check errno */
-        /* For timeout, just return 0 */
+    if (tcp_sndbuf(ctx->client_pcb) < len) {
+        return 0;
     }
 
-    return received;
+    err = tcp_write(ctx->client_pcb, data, len, TCP_WRITE_FLAG_COPY);
+    if (err != ERR_OK) {
+        ctx->status.errors++;
+        return -1;
+    }
+    err = tcp_output(ctx->client_pcb);
+    if (err != ERR_OK) {
+        ctx->status.errors++;
+        return -1;
+    }
+    return (int)len;
 }
 
-/**
- * @brief Check if client is connected
- */
-bool tcp_server_is_connected(void)
+int tcp_server_recv(uint8_t instance, uint8_t *data, uint16_t max_len)
 {
-    return (client_socket >= 0);
+    uint16_t copied = 0u;
+    tcp_server_ctx_t *ctx;
+
+    if (instance >= TCP_SERVER_INSTANCE_COUNT || data == NULL || max_len == 0u) {
+        return -1;
+    }
+    ctx = &g_servers[instance];
+    while (copied < max_len && ctx->rx_tail != ctx->rx_head) {
+        data[copied++] = ctx->rx_ring[ctx->rx_tail];
+        ctx->rx_tail = (uint16_t)((ctx->rx_tail + 1u) % TCP_SERVER_RX_BUFFER_SIZE);
+    }
+    return (int)copied;
 }
 
-/**
- * @brief Get TCP Server status
- */
-void tcp_server_get_status(tcp_server_status_t *status)
+bool tcp_server_is_connected(uint8_t instance)
 {
-    if (status != NULL)
-    {
-        memcpy(status, &server_status, sizeof(tcp_server_status_t));
-    }
-}
-
-/**
- * @brief Get RX StreamBuffer handle
- */
-void *tcp_server_get_rx_stream(void)
-{
-    return rx_stream;
-}
-
-/**
- * @brief Get TX StreamBuffer handle
- */
-void *tcp_server_get_tx_stream(void)
-{
-    return tx_stream;
-}
-
-/**
- * @brief TCP Server task
- */
-void tcp_server_task(void *argument)
-{
-    const device_config_t *cfg;
-    tcp_server_config_t task_cfg;
-    struct sockaddr_in client_addr;
-    socklen_t addr_len;
-    uint8_t rx_buffer[256];
-    uint8_t tx_buffer[256];
-    int received;
-    size_t tx_len;
-    fd_set read_fds;
-    struct timeval tv;
-    int max_fd;
-    
-    (void)argument;
-    
-    /* Initialize server */
-    task_cfg.port = TCP_SERVER_DEFAULT_PORT;
-    task_cfg.auto_reconnect = true;
-    cfg = config_get();
-    if (cfg != NULL && cfg->server_port > 0)
-    {
-        task_cfg.port = cfg->server_port;
-    }
-    tcp_server_init(&task_cfg);
-    
-    /* Start server */
-    while (tcp_server_start() != 0)
-    {
-        vTaskDelay(pdMS_TO_TICKS(1000));
-    }
-    
-    while (1)
-    {
-        /* Check if we need to accept a new connection */
-        if (client_socket < 0 && listen_socket >= 0)
-        {
-            /* Use select with timeout to check for incoming connections */
-            FD_ZERO(&read_fds);
-            FD_SET(listen_socket, &read_fds);
-            tv.tv_sec = 0;
-            tv.tv_usec = 100000;  /* 100ms timeout */
-            
-            if (select(listen_socket + 1, &read_fds, NULL, NULL, &tv) > 0)
-            {
-                addr_len = sizeof(client_addr);
-                client_socket = accept(listen_socket, (struct sockaddr *)&client_addr, &addr_len);
-                if (client_socket >= 0)
-                {
-                    server_status.state = TCP_SERVER_STATE_CONNECTED;
-                    server_status.connections++;
-                }
-            }
-        }
-        
-        /* Handle data transfer if connected */
-        if (client_socket >= 0)
-        {
-            /* Check for data from TCP client */
-            FD_ZERO(&read_fds);
-            FD_SET(client_socket, &read_fds);
-            max_fd = client_socket;
-            tv.tv_sec = 0;
-            tv.tv_usec = 10000;  /* 10ms timeout */
-            
-            if (select(max_fd + 1, &read_fds, NULL, NULL, &tv) > 0)
-            {
-                if (FD_ISSET(client_socket, &read_fds))
-                {
-                    received = recv(client_socket, rx_buffer, sizeof(rx_buffer), 0);
-                    if (received > 0)
-                    {
-                        /* Forward to UART via stream buffer */
-                        xStreamBufferSend(rx_stream, rx_buffer, received, pdMS_TO_TICKS(10));
-                        server_status.rx_bytes += received;
-                    }
-                    else if (received == 0)
-                    {
-                        /* Connection closed */
-                        close(client_socket);
-                        client_socket = -1;
-                        server_status.state = TCP_SERVER_STATE_LISTENING;
-                    }
-                    else
-                    {
-                        /* Error */
-                        close(client_socket);
-                        client_socket = -1;
-                        server_status.state = TCP_SERVER_STATE_LISTENING;
-                        server_status.errors++;
-                    }
-                }
-            }
-            
-            /* Check for data from UART to send to TCP */
-            tx_len = xStreamBufferReceive(tx_stream, tx_buffer, sizeof(tx_buffer), 0);
-            if (tx_len > 0)
-            {
-                int sent = tcp_server_send_all(client_socket, tx_buffer, (uint16_t)tx_len);
-                if (sent > 0)
-                {
-                    server_status.tx_bytes += sent;
-                }
-                else if (sent < 0)
-                {
-                    /* Send error */
-                    close(client_socket);
-                    client_socket = -1;
-                    server_status.state = TCP_SERVER_STATE_LISTENING;
-                    server_status.errors++;
-                }
-            }
-        }
-        
-        /* Small delay to prevent tight loop */
-        vTaskDelay(pdMS_TO_TICKS(1));
+    return (instance < TCP_SERVER_INSTANCE_COUNT) && (g_servers[instance].client_pcb != NULL);
+}
+
+void tcp_server_get_status(uint8_t instance, tcp_server_status_t *status)
+{
+    if (instance < TCP_SERVER_INSTANCE_COUNT && status != NULL) {
+        *status = g_servers[instance].status;
     }
 }

App/tcp_server.h

@@ -1,43 +1,33 @@
 /**
  * @file tcp_server.h
- * @brief TCP Server module for transparent transmission with UART2
+ * @brief Indexed lwIP RAW TCP server manager.
  */
 
 #ifndef __TCP_SERVER_H__
 #define __TCP_SERVER_H__
 
-#include <stdint.h>
 #include <stdbool.h>
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/* Default TCP Server port */
-#define TCP_SERVER_DEFAULT_PORT     8080
+#define TCP_SERVER_INSTANCE_COUNT    2u
+#define TCP_SERVER_RX_BUFFER_SIZE    512u
 
-/* Maximum number of simultaneous connections */
-#define TCP_SERVER_MAX_CONNECTIONS  1
-
-/* Buffer sizes */
-#define TCP_SERVER_RX_BUFFER_SIZE   512
-#define TCP_SERVER_TX_BUFFER_SIZE   512
-
-/* TCP Server state */
 typedef enum {
-    TCP_SERVER_STATE_IDLE,
+    TCP_SERVER_STATE_IDLE = 0,
     TCP_SERVER_STATE_LISTENING,
     TCP_SERVER_STATE_CONNECTED,
     TCP_SERVER_STATE_ERROR
 } tcp_server_state_t;
 
-/* TCP Server configuration */
 typedef struct {
     uint16_t port;
-    bool auto_reconnect;
-} tcp_server_config_t;
+    bool enabled;
+} tcp_server_instance_config_t;
 
-/* TCP Server status */
 typedef struct {
     tcp_server_state_t state;
     uint32_t rx_bytes;
@@ -46,71 +36,14 @@ typedef struct {
     uint32_t errors;
 } tcp_server_status_t;
 
-/**
- * @brief Initialize TCP Server module
- * @param config Server configuration
- * @return 0 on success, negative on error
- */
-int tcp_server_init(const tcp_server_config_t *config);
-
-/**
- * @brief Start TCP Server (begin listening)
- * @return 0 on success, negative on error
- */
-int tcp_server_start(void);
-
-/**
- * @brief Stop TCP Server
- * @return 0 on success, negative on error
- */
-int tcp_server_stop(void);
-
-/**
- * @brief Send data to connected client
- * @param data Data buffer
- * @param len Data length
- * @return Number of bytes sent, negative on error
- */
-int tcp_server_send(const uint8_t *data, uint16_t len);
-
-/**
- * @brief Receive data from connected client
- * @param data Data buffer
- * @param max_len Maximum length to receive
- * @param timeout_ms Timeout in milliseconds (0 = non-blocking)
- * @return Number of bytes received, 0 if no data, negative on error
- */
-int tcp_server_recv(uint8_t *data, uint16_t max_len, uint32_t timeout_ms);
-
-/**
- * @brief Check if client is connected
- * @return true if connected
- */
-bool tcp_server_is_connected(void);
-
-/**
- * @brief Get TCP Server status
- * @param status Pointer to status structure
- */
-void tcp_server_get_status(tcp_server_status_t *status);
-
-/**
- * @brief Get TCP Server StreamBuffer handle for UART integration
- * @return StreamBuffer handle for receiving data from TCP
- */
-void *tcp_server_get_rx_stream(void);
-
-/**
- * @brief Get TCP Server TX StreamBuffer handle for UART integration
- * @return StreamBuffer handle for sending data to TCP
- */
-void *tcp_server_get_tx_stream(void);
-
-/**
- * @brief TCP Server task function (for FreeRTOS)
- * @param argument Task argument (unused)
- */
-void tcp_server_task(void *argument);
+int tcp_server_init_all(void);
+int tcp_server_config(uint8_t instance, const tcp_server_instance_config_t *config);
+int tcp_server_start(uint8_t instance);
+int tcp_server_stop(uint8_t instance);
+int tcp_server_send(uint8_t instance, const uint8_t *data, uint16_t len);
+int tcp_server_recv(uint8_t instance, uint8_t *data, uint16_t max_len);
+bool tcp_server_is_connected(uint8_t instance);
+void tcp_server_get_status(uint8_t instance, tcp_server_status_t *status);
 
 #ifdef __cplusplus
 }

App/uart_trans.c

@@ -1,528 +1,388 @@
 /**
  * @file uart_trans.c
- * @brief UART transparent transmission module implementation
- * 
- * Uses DMA + IDLE interrupt for efficient variable-length data reception.
- * Integrates with TCP modules via FreeRTOS StreamBuffers.
+ * @brief Bare-metal UART DMA/IDLE transport and MUX helpers.
  */
 
 #include "uart_trans.h"
-#include "usart.h"
 
-#include "FreeRTOS.h"
-#include "task.h"
-#include "stream_buffer.h"
+#include "../Core/Inc/usart.h"
 
 #include <string.h>
 
-/*---------------------------------------------------------------------------
- * Private Definitions
- *---------------------------------------------------------------------------*/
+#define UART_MUX_SYNC  0x7Eu
+#define UART_MUX_TAIL  0x7Fu
 
-/* Channel context structure */
 typedef struct {
-    UART_HandleTypeDef *huart;          /* HAL UART handle */
-    DMA_HandleTypeDef  *hdma_rx;        /* DMA RX handle */
-    
-    uint8_t  rx_dma_buffer[UART_RX_DMA_BUFFER_SIZE];  /* DMA RX buffer */
-    uint8_t  tx_dma_buffer[UART_TX_DMA_BUFFER_SIZE];  /* DMA TX buffer */
-    
-    volatile uint16_t rx_read_index;    /* Last read position */
-    volatile bool     tx_busy;          /* TX in progress flag */
-    
-    StreamBufferHandle_t rx_stream;     /* From TCP (for UART TX) */
-    StreamBufferHandle_t tx_stream;     /* To TCP (from UART RX) */
-    
-    uart_config_t config;               /* UART configuration */
-    uart_stats_t  stats;                /* Statistics */
-    
+    UART_HandleTypeDef *huart;
+    uint8_t rx_dma_buffer[UART_RX_DMA_BUFFER_SIZE];
+    uint8_t tx_dma_buffer[UART_TX_DMA_BUFFER_SIZE];
+    uint8_t rx_ring[UART_RX_RING_BUFFER_SIZE];
+    uint8_t tx_ring[UART_TX_RING_BUFFER_SIZE];
+    volatile uint16_t rx_dma_read_index;
+    volatile uint16_t rx_head;
+    volatile uint16_t rx_tail;
+    volatile uint16_t tx_head;
+    volatile uint16_t tx_tail;
+    volatile uint16_t tx_dma_len;
+    volatile bool tx_busy;
+    uart_config_t config;
+    uart_stats_t stats;
     bool initialized;
     bool running;
 } uart_channel_ctx_t;
 
-/*---------------------------------------------------------------------------
- * Private Variables
- *---------------------------------------------------------------------------*/
-
 static uart_channel_ctx_t g_channels[UART_CHANNEL_MAX];
 
-/*---------------------------------------------------------------------------
- * Private Functions
- *---------------------------------------------------------------------------*/
+static uint16_t ring_used(uint16_t head, uint16_t tail, uint16_t size)
+{
+    return (head >= tail) ? (head - tail) : (size - tail + head);
+}
+
+static uint16_t ring_free(uint16_t head, uint16_t tail, uint16_t size)
+{
+    return (uint16_t)(size - ring_used(head, tail, size) - 1u);
+}
 
-/**
- * @brief Apply UART configuration
- */
 static int apply_uart_config(uart_channel_t channel)
 {
     uart_channel_ctx_t *ctx = &g_channels[channel];
-    UART_HandleTypeDef *huart = ctx->huart;
-    
-    if (huart == NULL)
-    {
+    if (ctx->huart == NULL) {
         return -1;
     }
 
-    /* Stop UART if running */
-    if (ctx->running)
-    {
-        HAL_UART_DMAStop(huart);
+    if (ctx->running) {
+        HAL_UART_DMAStop(ctx->huart);
+        ctx->running = false;
     }
 
-    /* Update UART parameters */
-    huart->Init.BaudRate = ctx->config.baudrate;
-    
-    /* Data bits */
-    if (ctx->config.data_bits == 9)
-    {
-        huart->Init.WordLength = UART_WORDLENGTH_9B;
-    }
-    else
-    {
-        huart->Init.WordLength = UART_WORDLENGTH_8B;
-    }
-    
-    /* Stop bits */
-    if (ctx->config.stop_bits == 2)
-    {
-        huart->Init.StopBits = UART_STOPBITS_2;
-    }
-    else
-    {
-        huart->Init.StopBits = UART_STOPBITS_1;
-    }
-    
-    /* Parity */
-    switch (ctx->config.parity)
-    {
-        case 1:
-            huart->Init.Parity = UART_PARITY_ODD;
-            break;
-        case 2:
-            huart->Init.Parity = UART_PARITY_EVEN;
-            break;
-        default:
-            huart->Init.Parity = UART_PARITY_NONE;
-            break;
-    }
-    
-    /* Reinitialize UART */
-    if (HAL_UART_Init(huart) != HAL_OK)
-    {
-        return -1;
-    }
-    
-    return 0;
+    ctx->huart->Init.BaudRate = ctx->config.baudrate;
+    ctx->huart->Init.WordLength = UART_WORDLENGTH_8B;
+    ctx->huart->Init.StopBits = UART_STOPBITS_1;
+    ctx->huart->Init.Parity = UART_PARITY_NONE;
+    return (HAL_UART_Init(ctx->huart) == HAL_OK) ? 0 : -1;
 }
 
-static void process_rx_data_from_isr(uart_channel_t channel, uint16_t end_index)
+static void process_rx_snapshot(uart_channel_t channel, uint16_t dma_write_index)
 {
     uart_channel_ctx_t *ctx = &g_channels[channel];
-    uint16_t start = ctx->rx_read_index;
-    uint16_t end = end_index;
-    uint16_t len;
-    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
 
-    if (start >= UART_RX_DMA_BUFFER_SIZE)
-    {
-        start = 0;
-    }
-
-    if (end > UART_RX_DMA_BUFFER_SIZE)
-    {
-        end = UART_RX_DMA_BUFFER_SIZE;
-    }
-
-    if (end >= start)
-    {
-        len = end - start;
-        if (len > 0 && ctx->tx_stream != NULL)
-        {
-            xStreamBufferSendFromISR(ctx->tx_stream,
-                                     &ctx->rx_dma_buffer[start],
-                                     len,
-                                     &xHigherPriorityTaskWoken);
-            ctx->stats.rx_bytes += len;
-            ctx->stats.rx_packets++;
-        }
-    }
-    else
-    {
-        len = UART_RX_DMA_BUFFER_SIZE - start;
-        if (len > 0 && ctx->tx_stream != NULL)
-        {
-            xStreamBufferSendFromISR(ctx->tx_stream,
-                                     &ctx->rx_dma_buffer[start],
-                                     len,
-                                     &xHigherPriorityTaskWoken);
-            ctx->stats.rx_bytes += len;
+    while (ctx->rx_dma_read_index != dma_write_index) {
+        uint16_t next_head = (uint16_t)((ctx->rx_head + 1u) % UART_RX_RING_BUFFER_SIZE);
+        if (next_head == ctx->rx_tail) {
+            ctx->stats.errors++;
+            break;
         }
 
-        if (end > 0 && ctx->tx_stream != NULL)
-        {
-            xStreamBufferSendFromISR(ctx->tx_stream,
-                                     ctx->rx_dma_buffer,
-                                     end,
-                                     &xHigherPriorityTaskWoken);
-            ctx->stats.rx_bytes += end;
-        }
-        ctx->stats.rx_packets++;
+        ctx->rx_ring[ctx->rx_head] = ctx->rx_dma_buffer[ctx->rx_dma_read_index];
+        ctx->rx_head = next_head;
+        ctx->rx_dma_read_index = (uint16_t)((ctx->rx_dma_read_index + 1u) % UART_RX_DMA_BUFFER_SIZE);
+        ctx->stats.rx_bytes++;
     }
-
-    ctx->rx_read_index = (end == UART_RX_DMA_BUFFER_SIZE) ? 0 : end;
-    portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
 }
 
-/*---------------------------------------------------------------------------
- * Public Functions
- *---------------------------------------------------------------------------*/
+static void kick_tx(uart_channel_t channel)
+{
+    uart_channel_ctx_t *ctx = &g_channels[channel];
+    uint16_t available;
+    uint16_t chunk;
+
+    if (!ctx->running || ctx->tx_busy) {
+        return;
+    }
+
+    available = ring_used(ctx->tx_head, ctx->tx_tail, UART_TX_RING_BUFFER_SIZE);
+    if (available == 0u) {
+        return;
+    }
+
+    chunk = available;
+    if (chunk > UART_TX_DMA_BUFFER_SIZE) {
+        chunk = UART_TX_DMA_BUFFER_SIZE;
+    }
+
+    for (uint16_t i = 0; i < chunk; ++i) {
+        ctx->tx_dma_buffer[i] = ctx->tx_ring[ctx->tx_tail];
+        ctx->tx_tail = (uint16_t)((ctx->tx_tail + 1u) % UART_TX_RING_BUFFER_SIZE);
+    }
+
+    ctx->tx_dma_len = chunk;
+    ctx->tx_busy = true;
+    ctx->stats.tx_packets++;
+
+    if (HAL_UART_Transmit_DMA(ctx->huart, ctx->tx_dma_buffer, chunk) != HAL_OK) {
+        ctx->tx_busy = false;
+        ctx->stats.errors++;
+    }
+}
 
-/**
- * @brief Initialize UART transparent transmission module
- */
 int uart_trans_init(void)
 {
-    /* Initialize Server channel (UART2) */
-    memset(&g_channels[UART_CHANNEL_SERVER], 0, sizeof(uart_channel_ctx_t));
-    g_channels[UART_CHANNEL_SERVER].huart = &huart2;
-    g_channels[UART_CHANNEL_SERVER].config.baudrate = UART_DEFAULT_BAUDRATE;
-    g_channels[UART_CHANNEL_SERVER].config.data_bits = UART_DEFAULT_DATA_BITS;
-    g_channels[UART_CHANNEL_SERVER].config.stop_bits = UART_DEFAULT_STOP_BITS;
-    g_channels[UART_CHANNEL_SERVER].config.parity = UART_DEFAULT_PARITY;
-    g_channels[UART_CHANNEL_SERVER].initialized = true;
-    
-    /* Initialize Client channel (UART3) */
-    memset(&g_channels[UART_CHANNEL_CLIENT], 0, sizeof(uart_channel_ctx_t));
-    g_channels[UART_CHANNEL_CLIENT].huart = &huart3;
-    g_channels[UART_CHANNEL_CLIENT].config.baudrate = UART_DEFAULT_BAUDRATE;
-    g_channels[UART_CHANNEL_CLIENT].config.data_bits = UART_DEFAULT_DATA_BITS;
-    g_channels[UART_CHANNEL_CLIENT].config.stop_bits = UART_DEFAULT_STOP_BITS;
-    g_channels[UART_CHANNEL_CLIENT].config.parity = UART_DEFAULT_PARITY;
-    g_channels[UART_CHANNEL_CLIENT].initialized = true;
-    
+    memset(g_channels, 0, sizeof(g_channels));
+    g_channels[UART_CHANNEL_U0].huart = &huart2;
+    g_channels[UART_CHANNEL_U1].huart = &huart3;
+    g_channels[UART_CHANNEL_U0].config.baudrate = UART_DEFAULT_BAUDRATE;
+    g_channels[UART_CHANNEL_U1].config.baudrate = UART_DEFAULT_BAUDRATE;
+    g_channels[UART_CHANNEL_U0].initialized = true;
+    g_channels[UART_CHANNEL_U1].initialized = true;
     return 0;
 }
 
-/**
- * @brief Configure UART channel parameters
- */
 int uart_trans_config(uart_channel_t channel, const uart_config_t *config)
 {
-    if (channel >= UART_CHANNEL_MAX || config == NULL)
-    {
+    if (channel >= UART_CHANNEL_MAX || config == NULL) {
         return -1;
     }
-    
-    uart_channel_ctx_t *ctx = &g_channels[channel];
-    
-    memcpy(&ctx->config, config, sizeof(uart_config_t));
-    
-    /* Apply configuration if already initialized */
-    if (ctx->initialized)
-    {
-        return apply_uart_config(channel);
-    }
-    
-    return 0;
+    g_channels[channel].config = *config;
+    return apply_uart_config(channel);
 }
 
-/**
- * @brief Start UART reception
- */
 int uart_trans_start(uart_channel_t channel)
 {
-    if (channel >= UART_CHANNEL_MAX)
-    {
+    uart_channel_ctx_t *ctx;
+
+    if (channel >= UART_CHANNEL_MAX) {
         return -1;
     }
 
-    uart_channel_ctx_t *ctx = &g_channels[channel];
-    
-    if (!ctx->initialized || ctx->huart == NULL)
-    {
+    ctx = &g_channels[channel];
+    if (!ctx->initialized || ctx->huart == NULL) {
         return -1;
     }
 
-    /* Reset read index */
-    ctx->rx_read_index = 0;
+    ctx->rx_dma_read_index = 0u;
+    ctx->rx_head = 0u;
+    ctx->rx_tail = 0u;
+    ctx->tx_head = 0u;
+    ctx->tx_tail = 0u;
+    ctx->tx_dma_len = 0u;
     ctx->tx_busy = false;
+    memset(&ctx->stats, 0, sizeof(ctx->stats));
 
-    /* Enable IDLE interrupt */
     __HAL_UART_ENABLE_IT(ctx->huart, UART_IT_IDLE);
-    
-    /* Start DMA reception (circular mode) */
-    HAL_UART_Receive_DMA(ctx->huart, ctx->rx_dma_buffer, UART_RX_DMA_BUFFER_SIZE);
+    if (HAL_UART_Receive_DMA(ctx->huart, ctx->rx_dma_buffer, UART_RX_DMA_BUFFER_SIZE) != HAL_OK) {
+        return -1;
+    }
 
     ctx->running = true;
-    
     return 0;
 }
 
-/**
- * @brief Stop UART reception
- */
 int uart_trans_stop(uart_channel_t channel)
 {
-    if (channel >= UART_CHANNEL_MAX)
-    {
+    if (channel >= UART_CHANNEL_MAX) {
         return -1;
     }
-    
-    uart_channel_ctx_t *ctx = &g_channels[channel];
-    
-    if (ctx->huart == NULL)
-    {
-        return -1;
-    }
-    
-    /* Disable IDLE interrupt */
-    __HAL_UART_DISABLE_IT(ctx->huart, UART_IT_IDLE);
-    
-    /* Stop DMA */
-    HAL_UART_DMAStop(ctx->huart);
-    
-    ctx->running = false;
-    
+    HAL_UART_DMAStop(g_channels[channel].huart);
+    g_channels[channel].running = false;
+    g_channels[channel].tx_busy = false;
     return 0;
 }
 
-/**
- * @brief Set StreamBuffer handles
- */
-void uart_trans_set_streams(uart_channel_t channel, 
-                            void *rx_stream, 
-                            void *tx_stream)
+void uart_trans_poll(void)
 {
-    if (channel >= UART_CHANNEL_MAX)
-    {
-        return;
-    }
-    
-    g_channels[channel].rx_stream = (StreamBufferHandle_t)rx_stream;
-    g_channels[channel].tx_stream = (StreamBufferHandle_t)tx_stream;
+    kick_tx(UART_CHANNEL_U0);
+    kick_tx(UART_CHANNEL_U1);
+}
+
+uint16_t uart_trans_rx_available(uart_channel_t channel)
+{
+    if (channel >= UART_CHANNEL_MAX) {
+        return 0u;
+    }
+    return ring_used(g_channels[channel].rx_head, g_channels[channel].rx_tail, UART_RX_RING_BUFFER_SIZE);
+}
+
+uint16_t uart_trans_read(uart_channel_t channel, uint8_t *data, uint16_t max_len)
+{
+    uart_channel_ctx_t *ctx;
+    uint16_t copied = 0u;
+
+    if (channel >= UART_CHANNEL_MAX || data == NULL || max_len == 0u) {
+        return 0u;
+    }
+
+    ctx = &g_channels[channel];
+    while (copied < max_len && ctx->rx_tail != ctx->rx_head) {
+        data[copied++] = ctx->rx_ring[ctx->rx_tail];
+        ctx->rx_tail = (uint16_t)((ctx->rx_tail + 1u) % UART_RX_RING_BUFFER_SIZE);
+    }
+    if (copied > 0u) {
+        ctx->stats.rx_packets++;
+    }
+    return copied;
+}
+
+uint16_t uart_trans_write(uart_channel_t channel, const uint8_t *data, uint16_t len)
+{
+    uart_channel_ctx_t *ctx;
+    uint16_t written = 0u;
+
+    if (channel >= UART_CHANNEL_MAX || data == NULL || len == 0u) {
+        return 0u;
+    }
+
+    ctx = &g_channels[channel];
+    while (written < len && ring_free(ctx->tx_head, ctx->tx_tail, UART_TX_RING_BUFFER_SIZE) > 0u) {
+        ctx->tx_ring[ctx->tx_head] = data[written++];
+        ctx->tx_head = (uint16_t)((ctx->tx_head + 1u) % UART_TX_RING_BUFFER_SIZE);
+    }
+
+    if (written < len) {
+        ctx->stats.errors++;
+    }
+
+    kick_tx(channel);
+    return written;
 }
 
-/**
- * @brief Get UART statistics
- */
 void uart_trans_get_stats(uart_channel_t channel, uart_stats_t *stats)
 {
-    if (channel >= UART_CHANNEL_MAX || stats == NULL)
-    {
-        return;
+    if (channel < UART_CHANNEL_MAX && stats != NULL) {
+        *stats = g_channels[channel].stats;
     }
-    
-    memcpy(stats, &g_channels[channel].stats, sizeof(uart_stats_t));
 }
 
-/**
- * @brief Reset UART statistics
- */
 void uart_trans_reset_stats(uart_channel_t channel)
 {
-    if (channel >= UART_CHANNEL_MAX)
-    {
-        return;
+    if (channel < UART_CHANNEL_MAX) {
+        memset(&g_channels[channel].stats, 0, sizeof(g_channels[channel].stats));
     }
-    
-    memset(&g_channels[channel].stats, 0, sizeof(uart_stats_t));
 }
 
-/**
- * @brief UART IDLE interrupt handler
- */
 void uart_trans_idle_handler(uart_channel_t channel)
 {
-    if (channel >= UART_CHANNEL_MAX)
-    {
+    UART_HandleTypeDef *huart;
+    uint16_t dma_write_index;
+
+    if (channel >= UART_CHANNEL_MAX) {
         return;
     }
-    
-    uart_channel_ctx_t *ctx = &g_channels[channel];
-    
-    if (!ctx->running || ctx->huart == NULL)
-    {
-        return;
-    }
-    
-    /* Get current DMA position */
-    uint16_t dma_counter = __HAL_DMA_GET_COUNTER(ctx->huart->hdmarx);
-    uint16_t current_pos = UART_RX_DMA_BUFFER_SIZE - dma_counter;
-    
-    /* Process received data */
-    if (current_pos != ctx->rx_read_index)
-    {
-        process_rx_data_from_isr(channel, current_pos);
+    huart = g_channels[channel].huart;
+    g_channels[channel].stats.idle_events++;
+    dma_write_index = (uint16_t)(UART_RX_DMA_BUFFER_SIZE - __HAL_DMA_GET_COUNTER(huart->hdmarx));
+    if (dma_write_index >= UART_RX_DMA_BUFFER_SIZE) {
+        dma_write_index = 0u;
     }
+    process_rx_snapshot(channel, dma_write_index);
 }
 
 void uart_trans_rx_half_cplt_handler(uart_channel_t channel)
 {
-    if (channel >= UART_CHANNEL_MAX)
-    {
+    if (channel >= UART_CHANNEL_MAX) {
         return;
     }
-
-    uart_channel_ctx_t *ctx = &g_channels[channel];
-    if (!ctx->running || ctx->huart == NULL)
-    {
-        return;
-    }
-
-    uint16_t dma_counter = __HAL_DMA_GET_COUNTER(ctx->huart->hdmarx);
-    uint16_t current_pos = UART_RX_DMA_BUFFER_SIZE - dma_counter;
-
-    if (current_pos != ctx->rx_read_index)
-    {
-        process_rx_data_from_isr(channel, current_pos);
-    }
+    g_channels[channel].stats.rx_half_events++;
+    process_rx_snapshot(channel, UART_RX_DMA_BUFFER_SIZE / 2u);
 }
 
-/**
- * @brief UART DMA RX complete callback (buffer half/full)
- */
 void uart_trans_rx_cplt_handler(uart_channel_t channel)
 {
-    /* In circular mode, this is called when buffer is full */
-    /* The IDLE handler already processes data continuously */
-    /* This is a safety handler for high-speed continuous data */
-    
-    if (channel >= UART_CHANNEL_MAX)
-    {
+    if (channel >= UART_CHANNEL_MAX) {
         return;
     }
-    
-    uart_channel_ctx_t *ctx = &g_channels[channel];
-    
-    if (!ctx->running)
-    {
-        return;
-    }
-    
-    uint16_t dma_counter = __HAL_DMA_GET_COUNTER(ctx->huart->hdmarx);
-    uint16_t current_pos = UART_RX_DMA_BUFFER_SIZE - dma_counter;
-
-    if (current_pos != ctx->rx_read_index)
-    {
-        process_rx_data_from_isr(channel, current_pos);
-    }
+    g_channels[channel].stats.rx_full_events++;
+    process_rx_snapshot(channel, 0u);
 }
 
-/**
- * @brief UART DMA TX complete callback
- */
 void uart_trans_tx_cplt_handler(uart_channel_t channel)
 {
-    if (channel >= UART_CHANNEL_MAX)
-    {
+    if (channel >= UART_CHANNEL_MAX) {
         return;
     }
-    
     g_channels[channel].tx_busy = false;
+    g_channels[channel].stats.tx_bytes += g_channels[channel].tx_dma_len;
+    g_channels[channel].tx_dma_len = 0u;
+    kick_tx(channel);
 }
 
-/**
- * @brief Server transparent transmission task (UART2 <-> TCP Server)
- */
-void uart_server_trans_task(void *argument)
+bool uart_mux_try_extract_frame(uart_channel_t channel, uart_mux_frame_t *frame)
 {
-    uart_channel_ctx_t *ctx = &g_channels[UART_CHANNEL_SERVER];
-    uint8_t tx_buffer[128];
-    size_t len;
+    uint8_t sync_byte;
+    uint8_t header[4];
+    uint16_t available;
+    uint16_t payload_len;
 
-    (void)argument;
-    
-    /* Wait for streams to be set */
-    while (ctx->rx_stream == NULL || ctx->tx_stream == NULL)
-    {
-        vTaskDelay(pdMS_TO_TICKS(100));
+    if (channel >= UART_CHANNEL_MAX || frame == NULL) {
+        return false;
     }
 
-    /* Start UART reception */
-    uart_trans_start(UART_CHANNEL_SERVER);
+    available = uart_trans_rx_available(channel);
+    if (available < 6u) {
+        return false;
+    }
 
-    while (1)
-    {
-        /* Check for data from TCP to send to UART */
-        if (!ctx->tx_busy && ctx->rx_stream != NULL)
-        {
-            len = xStreamBufferReceive(ctx->rx_stream, tx_buffer, 
-                                       sizeof(tx_buffer), pdMS_TO_TICKS(10));
-            if (len > 0)
-            {
-                /* Copy to DMA buffer and send */
-                memcpy(ctx->tx_dma_buffer, tx_buffer, len);
-                ctx->tx_busy = true;
+    /* Scan for SYNC byte (0x7E) — discard non-matching bytes one at a time */
+    if (uart_trans_read(channel, &sync_byte, 1u) != 1u) {
+        return false;
+    }
+    if (sync_byte != UART_MUX_SYNC) {
+        return false;
+    }
 
-                if (HAL_UART_Transmit_DMA(ctx->huart, ctx->tx_dma_buffer, len) != HAL_OK)
-                {
-                    ctx->tx_busy = false;
-                    ctx->stats.errors++;
-                }
-                else
-                {
-                    ctx->stats.tx_bytes += len;
-                    ctx->stats.tx_packets++;
-                }
-            }
-        }
-        else
-        {
-            /* TX busy or no stream, wait a bit */
-            vTaskDelay(pdMS_TO_TICKS(1));
+    /* Need at least: 2(len) + 1(src) + 1(dst) + payload + 1(tail) = 5 + payload */
+    available = uart_trans_rx_available(channel);
+    if (available < 4u) {
+        return false;
+    }
+
+    if (uart_trans_read(channel, header, sizeof(header)) != sizeof(header)) {
+        return false;
+    }
+
+    payload_len = (uint16_t)(((uint16_t)header[0] << 8) | header[1]);
+    if (payload_len > sizeof(frame->payload)) {
+        return false;
+    }
+    if (uart_trans_rx_available(channel) < (uint16_t)(payload_len + 1u)) {
+        return false;
+    }
+
+    frame->src_id = header[2];
+    frame->dst_mask = header[3];
+    frame->payload_len = payload_len;
+    if (payload_len > 0u) {
+        if (uart_trans_read(channel, frame->payload, payload_len) != payload_len) {
+            return false;
         }
     }
+
+    {
+        uint8_t tail = 0u;
+        if (uart_trans_read(channel, &tail, 1u) != 1u || tail != UART_MUX_TAIL) {
+            return false;
+        }
+    }
+
+    return true;
 }
 
-/**
- * @brief Client transparent transmission task (UART3 <-> TCP Client)
- */
-void uart_client_trans_task(void *argument)
+bool uart_mux_encode_frame(uint8_t src_id,
+                           uint8_t dst_mask,
+                           const uint8_t *payload,
+                           uint16_t payload_len,
+                           uint8_t *out,
+                           uint16_t *out_len,
+                           uint16_t out_capacity)
 {
-    uart_channel_ctx_t *ctx = &g_channels[UART_CHANNEL_CLIENT];
-    uint8_t tx_buffer[128];
-    size_t len;
+    uint16_t frame_len;
 
-    (void)argument;
-    
-    /* Wait for streams to be set */
-    while (ctx->rx_stream == NULL || ctx->tx_stream == NULL)
-    {
-        vTaskDelay(pdMS_TO_TICKS(100));
+    if (out == NULL || out_len == NULL) {
+        return false;
+    }
+    frame_len = (uint16_t)(payload_len + 6u);
+    if (frame_len > out_capacity) {
+        return false;
     }
 
-    /* Start UART reception */
-    uart_trans_start(UART_CHANNEL_CLIENT);
-    
-    while (1)
-    {
-        /* Check for data from TCP to send to UART */
-        if (!ctx->tx_busy && ctx->rx_stream != NULL)
-        {
-            len = xStreamBufferReceive(ctx->rx_stream, tx_buffer, 
-                                       sizeof(tx_buffer), pdMS_TO_TICKS(10));
-            if (len > 0)
-            {
-                /* Copy to DMA buffer and send */
-                memcpy(ctx->tx_dma_buffer, tx_buffer, len);
-                ctx->tx_busy = true;
-                
-                if (HAL_UART_Transmit_DMA(ctx->huart, ctx->tx_dma_buffer, len) != HAL_OK)
-                {
-                    ctx->tx_busy = false;
-                    ctx->stats.errors++;
-                }
-                else
-                {
-                    ctx->stats.tx_bytes += len;
-                    ctx->stats.tx_packets++;
-                }
-            }
-        }
-        else
-        {
-            /* TX busy or no stream, wait a bit */
-            vTaskDelay(pdMS_TO_TICKS(1));
-        }
+    out[0] = UART_MUX_SYNC;
+    out[1] = (uint8_t)(payload_len >> 8);
+    out[2] = (uint8_t)(payload_len & 0xFFu);
+    out[3] = src_id;
+    out[4] = dst_mask;
+    if (payload_len > 0u && payload != NULL) {
+        memcpy(&out[5], payload, payload_len);
     }
+    out[5 + payload_len] = UART_MUX_TAIL;
+    *out_len = frame_len;
+    return true;
 }

App/uart_trans.h

@@ -1,148 +1,74 @@
 /**
  * @file uart_trans.h
- * @brief UART transparent transmission module for TCP2UART
- * 
- * - UART2 <-> TCP Server (via StreamBuffer)
- * - UART3 <-> TCP Client (via StreamBuffer)
- * - DMA + IDLE interrupt for efficient reception
+ * @brief Bare-metal UART DMA/IDLE transport and MUX framing helpers.
  */
 
 #ifndef __UART_TRANS_H__
 #define __UART_TRANS_H__
 
-#include <stdint.h>
 #include <stdbool.h>
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/* UART channel definitions */
 typedef enum {
-    UART_CHANNEL_SERVER = 0,    /* UART2 - TCP Server channel */
-    UART_CHANNEL_CLIENT = 1,    /* UART3 - TCP Client channel */
+    UART_CHANNEL_U0 = 0,
+    UART_CHANNEL_U1 = 1,
     UART_CHANNEL_MAX
 } uart_channel_t;
 
-/* DMA buffer sizes */
-#define UART_RX_DMA_BUFFER_SIZE     128
-#define UART_TX_DMA_BUFFER_SIZE     128
+typedef struct {
+    uint8_t src_id;
+    uint8_t dst_mask;
+    uint16_t payload_len;
+    uint8_t payload[256];
+} uart_mux_frame_t;
+
+#define UART_RX_DMA_BUFFER_SIZE   256u
+#define UART_TX_DMA_BUFFER_SIZE   256u
+#define UART_RX_RING_BUFFER_SIZE  512u
+#define UART_TX_RING_BUFFER_SIZE  384u
+#define UART_DEFAULT_BAUDRATE     115200u
 
-/* UART configuration */
 typedef struct {
     uint32_t baudrate;
-    uint8_t  data_bits;     /* 8 or 9 */
-    uint8_t  stop_bits;     /* 1 or 2 */
-    uint8_t  parity;        /* 0=None, 1=Odd, 2=Even */
 } uart_config_t;
 
-/* Default configurations */
-#define UART_DEFAULT_BAUDRATE       115200
-#define UART_DEFAULT_DATA_BITS      8
-#define UART_DEFAULT_STOP_BITS      1
-#define UART_DEFAULT_PARITY         0
-
-/* UART statistics */
 typedef struct {
     uint32_t rx_bytes;
     uint32_t tx_bytes;
     uint32_t rx_packets;
     uint32_t tx_packets;
+    uint32_t idle_events;
+    uint32_t rx_half_events;
+    uint32_t rx_full_events;
     uint32_t errors;
 } uart_stats_t;
 
-/**
- * @brief Initialize UART transparent transmission module
- * @return 0 on success, negative on error
- */
 int uart_trans_init(void);
-
-/**
- * @brief Configure UART channel parameters
- * @param channel UART channel (SERVER or CLIENT)
- * @param config UART configuration
- * @return 0 on success, negative on error
- */
 int uart_trans_config(uart_channel_t channel, const uart_config_t *config);
-
-/**
- * @brief Start UART reception (enable DMA + IDLE interrupt)
- * @param channel UART channel
- * @return 0 on success, negative on error
- */
 int uart_trans_start(uart_channel_t channel);
-
-/**
- * @brief Stop UART reception
- * @param channel UART channel
- * @return 0 on success, negative on error
- */
 int uart_trans_stop(uart_channel_t channel);
-
-/**
- * @brief Set StreamBuffer handles for TCP integration
- * @param channel UART channel
- * @param rx_stream StreamBuffer to receive data from TCP (for UART TX)
- * @param tx_stream StreamBuffer to send data to TCP (from UART RX)
- */
-void uart_trans_set_streams(uart_channel_t channel, 
-                            void *rx_stream, 
-                            void *tx_stream);
-
-/**
- * @brief Get UART statistics
- * @param channel UART channel
- * @param stats Pointer to statistics structure
- */
+void uart_trans_poll(void);
+uint16_t uart_trans_rx_available(uart_channel_t channel);
+uint16_t uart_trans_read(uart_channel_t channel, uint8_t *data, uint16_t max_len);
+uint16_t uart_trans_write(uart_channel_t channel, const uint8_t *data, uint16_t len);
 void uart_trans_get_stats(uart_channel_t channel, uart_stats_t *stats);
-
-/**
- * @brief Reset UART statistics
- * @param channel UART channel
- */
 void uart_trans_reset_stats(uart_channel_t channel);
-
-/**
- * @brief UART IDLE interrupt handler - call from stm32f1xx_it.c
- * @param channel UART channel
- * 
- * Usage in stm32f1xx_it.c USART2_IRQHandler:
- *   if (__HAL_UART_GET_FLAG(&huart2, UART_FLAG_IDLE)) {
- *       __HAL_UART_CLEAR_IDLEFLAG(&huart2);
- *       uart_trans_idle_handler(UART_CHANNEL_SERVER);
- *   }
- */
 void uart_trans_idle_handler(uart_channel_t channel);
-
-/**
- * @brief UART DMA RX half complete callback - call from HAL callback
- * @param channel UART channel
- */
 void uart_trans_rx_half_cplt_handler(uart_channel_t channel);
-
-/**
- * @brief UART DMA RX complete callback - call from HAL callback
- * @param channel UART channel
- */
 void uart_trans_rx_cplt_handler(uart_channel_t channel);
-
-/**
- * @brief UART DMA TX complete callback - call from HAL callback
- * @param channel UART channel
- */
 void uart_trans_tx_cplt_handler(uart_channel_t channel);
-
-/**
- * @brief Server transparent transmission task (UART2 <-> TCP Server)
- * @param argument Task argument (unused)
- */
-void uart_server_trans_task(void *argument);
-
-/**
- * @brief Client transparent transmission task (UART3 <-> TCP Client)
- * @param argument Task argument (unused)
- */
-void uart_client_trans_task(void *argument);
+bool uart_mux_try_extract_frame(uart_channel_t channel, uart_mux_frame_t *frame);
+bool uart_mux_encode_frame(uint8_t src_id,
+                           uint8_t dst_mask,
+                           const uint8_t *payload,
+                           uint16_t payload_len,
+                           uint8_t *out,
+                           uint16_t *out_len,
+                           uint16_t out_capacity);
 
 #ifdef __cplusplus
 }

CH390_最终结论报告.md

@@ -0,0 +1,105 @@
+# CH390 最终结论报告
+
+## 结论
+
+本轮循环调试的最终结论是：
+
+1. 当前工程中的主要软件问题已经完成收敛和清理。
+2. CH390D 驱动、lwIP `netif`、ARP 与 ICMP 基本链路已经在实机上打通。
+3. 本轮最终根因已确认不是普通软件逻辑错误，而是 CH390D 相关供电滤波电容虚焊，导致供电不稳定。
+
+## 已完成的软件侧工作
+
+本轮已完成并验证的事项包括：
+
+1. 修复 PHY 访问无超时导致的永久卡死风险。
+2. 修复未初始化 IWDG 句柄刷新导致的 HardFault。
+3. 清理 CH390 运行时中断屏蔽范围，消除阻塞式 SPI 访问造成的运行时假死。
+4. 重构 CH390 运行时所有权，避免多层并发触达底层 SPI 路径。
+5. 在 `main()` 中移除重复 CH390 复位，避免启动阶段额外复位噪声。
+6. 清理已确认 warning 来源，避免无效变量继续污染构建结果。
+7. 增加 CH390 identity gate，避免在无效寄存器读回前继续执行默认配置和 PHY 初始化。
+8. 曾增加 bit-bang 诊断读用于快速隔离问题，该临时调试路径已在当前代码中移除。
+
+## 实机关键证据
+
+### 1. MCU 自身正常工作
+
+已验证：
+
+1. RTT 正常输出。
+2. 主循环正常运行。
+3. `TIM4` 心跳正常。
+4. 运行期不再出现此前已修复的 HardFault 和“长时间假死”症状。
+
+### 2. 最终硬件根因已定位
+
+最终实板排查结果：
+
+1. 板载一颗 CH390D 供电相关滤波电容存在虚焊。
+2. 该问题导致 CH390D 供电不稳定，表现为寄存器读写、链路状态和报文收发在调试过程中不一致。
+3. 修复硬件后，实机已观察到：
+   - `VID=0x1C00`、`PID=0x9151`、`REV=0x2B`
+   - PHY 寄存器稳定可读
+   - `lwIP netif` 能进入 `LINK_UP`
+   - 设备可接收 ARP request 并发出 ARP reply
+   - 设备可接收 ICMP Echo Request 并发出 Echo Reply
+
+### 3. 历史 bit-bang 对照结果（已归档）
+
+在早期调试中，曾绕过 STM32 硬件 SPI 外设、直接用 GPIO 软件时序读取 `VIDL/VIDH/PIDL/PIDH/CHIPR`，RTT 输出为：
+
+```text
+CH390 bitbang VIDL=0xFF VIDH=0xFF PIDL=0xFF PIDH=0xFF CHIPR=0xFF
+```
+
+该历史证据用于定位阶段，当前仅保留结论，不再保留对应代码路径。它说明：
+
+1. 在硬件未修复前，单看软件现象会误导排查方向。
+2. 电源完整性问题会放大为看似“SPI/IRQ/RX/TX 都可疑”的复合症状。
+
+## 外部参考对结论的支撑
+
+对公开 CH390 / DM9051 实现的对照结果表明：
+
+1. CH390 SPI 访问时序、模式选择和 RX SRAM 连续事务仍然值得严格对照参考实现。
+2. 但本项目最终问题并非“参考实现缺失”，而是硬件供电缺陷放大了调试噪声。
+3. 外部参考对软件排查有帮助，但不能替代板级供电与焊接检查。
+
+## 当前最可信判断
+
+最终确认的板级问题为：
+
+1. CH390D 供电滤波电容虚焊。
+2. 该虚焊导致供电稳定性不足，从而引出不稳定的寄存器读写、链路与收发行为。
+
+## 版本库状态
+
+本轮已创建一个阶段性 checkpoint commit：
+
+1. `1808f99` `fix: harden CH390 bring-up diagnostics`
+
+该提交记录了：
+
+1. warning 清理
+2. 移除重复复位
+3. CH390 早期 identity gate
+4. 链路变化稳定等待
+
+## 推荐的下一步
+
+后续更高价值的工作不再是继续怀疑 CH390 是否“完全不通”，而是：
+
+1. 在硬件问题修复后补充长时间稳定性测试。
+2. 验证 TCP Server / TCP Client 业务流量与桥接逻辑在修复硬件后的行为。
+3. 保持驱动层日志最小化，仅在重新排障时按需开启详细 RTT。
+
+## 收尾说明
+
+本轮循环的退出条件已经满足：软件主路径已验证，且硬件根因已定位。
+
+因此当前最合理的结论是：
+
+1. CH390D 驱动、lwIP `netif`、ARP 和 ICMP 基本链路已在实机打通。
+2. 本轮真正拦路的不是普通软件逻辑，而是板级供电滤波电容虚焊。
+3. 后续应在硬件修复后的稳定板卡上继续推进应用层联调与文档收口。

CMakeLists.txt

@@ -0,0 +1,68 @@
+cmake_minimum_required(VERSION 3.22)
+
+#
+# This file is generated only once,
+# and is not re-generated if converter is called multiple times.
+#
+# User is free to modify the file as much as necessary
+#
+
+# Setup compiler settings
+set(CMAKE_C_STANDARD 11)
+set(CMAKE_C_STANDARD_REQUIRED ON)
+set(CMAKE_C_EXTENSIONS ON)
+
+
+# Define the build type
+if(NOT CMAKE_BUILD_TYPE)
+    set(CMAKE_BUILD_TYPE "Debug")
+endif()
+
+# Set the project name
+set(CMAKE_PROJECT_NAME TCP2UART)
+
+# Enable compile command to ease indexing with e.g. clangd
+set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE)
+
+# Core project settings
+project(${CMAKE_PROJECT_NAME})
+message("Build type: " ${CMAKE_BUILD_TYPE})
+
+# Enable CMake support for ASM and C languages
+enable_language(C ASM)
+
+# Create an executable object type
+add_executable(${CMAKE_PROJECT_NAME})
+
+# Add STM32CubeMX generated sources
+add_subdirectory(cmake/stm32cubemx)
+
+# Link directories setup
+target_link_directories(${CMAKE_PROJECT_NAME} PRIVATE
+    # Add user defined library search paths
+)
+
+# Add sources to executable
+target_sources(${CMAKE_PROJECT_NAME} PRIVATE
+    # Add user sources here
+)
+
+# Add include paths
+target_include_directories(${CMAKE_PROJECT_NAME} PRIVATE
+    # Add user defined include paths
+)
+
+# Add project symbols (macros)
+target_compile_definitions(${CMAKE_PROJECT_NAME} PRIVATE
+    # Add user defined symbols
+)
+
+# Remove wrong libob.a library dependency when using cpp files
+list(REMOVE_ITEM CMAKE_C_IMPLICIT_LINK_LIBRARIES ob)
+
+# Add linked libraries
+target_link_libraries(${CMAKE_PROJECT_NAME}
+    stm32cubemx
+
+    # Add user defined libraries
+)

CMakePresets.json

@@ -0,0 +1,38 @@
+{
+    "version": 3,
+    "configurePresets": [
+        {
+            "name": "default",
+            "hidden": true,
+            "generator": "Ninja",
+            "binaryDir": "${sourceDir}/build/${presetName}",
+		    "toolchainFile": "${sourceDir}/cmake/gcc-arm-none-eabi.cmake",
+            "cacheVariables": {
+            }
+        },
+        {
+            "name": "Debug",
+            "inherits": "default",
+            "cacheVariables": {
+                "CMAKE_BUILD_TYPE": "Debug"
+            }
+        },
+        {
+            "name": "Release",
+            "inherits": "default",
+            "cacheVariables": {
+                "CMAKE_BUILD_TYPE": "Release"
+            }
+        }
+    ],
+    "buildPresets": [
+        {
+            "name": "Debug",
+            "configurePreset": "Debug"
+        },
+        {
+            "name": "Release",
+            "configurePreset": "Release"
+        }
+    ]
+}

Core/Inc/main.h

@@ -53,6 +53,7 @@ extern "C" {
 void Error_Handler(void);
 
 /* USER CODE BEGIN EFP */
+void Debug_TrapWithRttHint(const char *tag);
 
 /* USER CODE END EFP */
 

Core/Inc/stm32f1xx_hal_conf.h

@@ -64,7 +64,7 @@
 /*#define HAL_SMARTCARD_MODULE_ENABLED   */
 #define HAL_SPI_MODULE_ENABLED
 /*#define HAL_SRAM_MODULE_ENABLED   */
-/*#define HAL_TIM_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
 #define HAL_UART_MODULE_ENABLED
 /*#define HAL_USART_MODULE_ENABLED   */
 /*#define HAL_WWDG_MODULE_ENABLED   */

Core/Inc/stm32f1xx_it.h

@@ -59,6 +59,7 @@ void DMA1_Channel4_IRQHandler(void);
 void DMA1_Channel5_IRQHandler(void);
 void DMA1_Channel6_IRQHandler(void);
 void DMA1_Channel7_IRQHandler(void);
+void TIM4_IRQHandler(void);
 void SPI1_IRQHandler(void);
 void USART1_IRQHandler(void);
 void USART2_IRQHandler(void);

Core/Inc/tim.h

@@ -0,0 +1,41 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.h
+  * @brief   This file contains all the function prototypes for the tim.c file
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TIM_H__
+#define __TIM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern TIM_HandleTypeDef htim4;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_TIM4_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_H__ */
+

Core/Src/freertos.c

@@ -1,370 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * File Name          : freertos.c
-  * Description        : Code for freertos applications
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2026 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-/* USER CODE END Header */
-
-/* Includes ------------------------------------------------------------------*/
-#include "FreeRTOS.h"
-#include "task.h"
-#include "main.h"
-#include "cmsis_os.h"
-
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-#include "semphr.h"
-#include "stream_buffer.h"
-
-/* Application modules */
-#include "tcp_server.h"
-#include "tcp_client.h"
-#include "uart_trans.h"
-#include "config.h"
-#include "ethernetif.h"
-
-/* LwIP includes */
-#include "lwip/tcpip.h"
-#include "lwip/ip4_addr.h"
-#include "lwip/dhcp.h"
-#include "lwip/timeouts.h"
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN PTD */
-
-/* USER CODE END PTD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN PD */
-/* Task stack sizes (words, not bytes) */
-#define LWIP_TASK_STACK_SIZE        384
-#define TCP_SERVER_TASK_STACK_SIZE  320
-#define TCP_CLIENT_TASK_STACK_SIZE  320
-#define UART_TRANS_TASK_STACK_SIZE  192
-#define CONFIG_TASK_STACK_SIZE      256
-#define DEFAULT_TASK_STACK_SIZE     128
-
-/* Task priorities */
-#define LWIP_TASK_PRIORITY          (osPriorityAboveNormal)
-#define TCP_SERVER_TASK_PRIORITY    (osPriorityNormal)
-#define TCP_CLIENT_TASK_PRIORITY    (osPriorityNormal)
-#define UART_TRANS_TASK_PRIORITY    (osPriorityNormal)
-#define CONFIG_TASK_PRIORITY        (osPriorityBelowNormal)
-#define DEFAULT_TASK_PRIORITY       (osPriorityLow)
-/* USER CODE END PD */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN PM */
-
-/* USER CODE END PM */
-
-/* Private variables ---------------------------------------------------------*/
-/* USER CODE BEGIN Variables */
-/* Task handles */
-TaskHandle_t lwipTaskHandle = NULL;
-TaskHandle_t tcpServerTaskHandle = NULL;
-TaskHandle_t tcpClientTaskHandle = NULL;
-TaskHandle_t uartServerTransTaskHandle = NULL;
-TaskHandle_t uartClientTransTaskHandle = NULL;
-TaskHandle_t configTaskHandle = NULL;
-
-/* SPI mutex for CH390 access */
-SemaphoreHandle_t ch390SpiMutex = NULL;
-
-/* CH390 interrupt notification semaphore */
-SemaphoreHandle_t ch390IntSemaphore = NULL;
-/* USER CODE END Variables */
-
-/* Definitions for defaultTask */
-osThreadId_t defaultTaskHandle;
-const osThreadAttr_t defaultTask_attributes = {
-  .name = "defaultTask",
-  .stack_size = DEFAULT_TASK_STACK_SIZE * 4,
-  .priority = (osPriority_t) DEFAULT_TASK_PRIORITY,
-};
-
-/* Private function prototypes -----------------------------------------------*/
-/* USER CODE BEGIN FunctionPrototypes */
-void LwIPTask(void *argument);
-/* USER CODE END FunctionPrototypes */
-
-void StartDefaultTask(void *argument);
-
-void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */
-
-/**
-  * @brief  FreeRTOS initialization
-  * @param  None
-  * @retval None
-  */
-void MX_FREERTOS_Init(void) {
-  /* USER CODE BEGIN Init */
-
-  /* USER CODE END Init */
-
-  /* USER CODE BEGIN RTOS_MUTEX */
-  /* Create SPI mutex for CH390 access */
-  ch390SpiMutex = xSemaphoreCreateMutex();
-  configASSERT(ch390SpiMutex != NULL);
-  /* USER CODE END RTOS_MUTEX */
-
-  /* USER CODE BEGIN RTOS_SEMAPHORES */
-  /* Create CH390 interrupt notification semaphore */
-  ch390IntSemaphore = xSemaphoreCreateBinary();
-  configASSERT(ch390IntSemaphore != NULL);
-  /* USER CODE END RTOS_SEMAPHORES */
-
-  /* USER CODE BEGIN RTOS_TIMERS */
-  /* start timers, add new ones, ... */
-  /* USER CODE END RTOS_TIMERS */
-
-  /* USER CODE BEGIN RTOS_QUEUES */
-  /* add queues, ... */
-  /* USER CODE END RTOS_QUEUES */
-
-  /* Create the thread(s) */
-  /* creation of defaultTask */
-  defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
-
-  /* USER CODE BEGIN RTOS_THREADS */
-  BaseType_t task_created;
-
-  /* Create LwIP task (handles network stack + TCP server/client) */
-  task_created = xTaskCreate(LwIPTask, "LwIP", LWIP_TASK_STACK_SIZE, NULL,
-                             tskIDLE_PRIORITY + 3, &lwipTaskHandle);
-  configASSERT(task_created == pdPASS);
-  
-  /* Create TCP Server task */
-  task_created = xTaskCreate(tcp_server_task, "TCPServer", TCP_SERVER_TASK_STACK_SIZE, NULL,
-                             tskIDLE_PRIORITY + 2, &tcpServerTaskHandle);
-  configASSERT(task_created == pdPASS);
-  
-  /* Create TCP Client task */
-  task_created = xTaskCreate(tcp_client_task, "TCPClient", TCP_CLIENT_TASK_STACK_SIZE, NULL,
-                             tskIDLE_PRIORITY + 2, &tcpClientTaskHandle);
-  configASSERT(task_created == pdPASS);
-  
-  /* Create UART Server transparent transmission task */
-  task_created = xTaskCreate(uart_server_trans_task, "UartSrvTx", UART_TRANS_TASK_STACK_SIZE, NULL,
-                             tskIDLE_PRIORITY + 2, &uartServerTransTaskHandle);
-  configASSERT(task_created == pdPASS);
-  
-  /* Create UART Client transparent transmission task */
-  task_created = xTaskCreate(uart_client_trans_task, "UartCliTx", UART_TRANS_TASK_STACK_SIZE, NULL,
-                             tskIDLE_PRIORITY + 2, &uartClientTransTaskHandle);
-  configASSERT(task_created == pdPASS);
-  
-  /* Create Configuration task (AT commands via UART1) */
-  task_created = xTaskCreate(config_task, "Config", CONFIG_TASK_STACK_SIZE, NULL,
-                             tskIDLE_PRIORITY + 1, &configTaskHandle);
-  configASSERT(task_created == pdPASS);
-  /* USER CODE END RTOS_THREADS */
-
-  /* USER CODE BEGIN RTOS_EVENTS */
-  /* add events, ... */
-  /* USER CODE END RTOS_EVENTS */
-
-}
-
-/* USER CODE BEGIN Header_StartDefaultTask */
-/**
-  * @brief  Function implementing the defaultTask thread.
-  *         LED blinking for system status indication.
-  * @param  argument: Not used
-  * @retval None
-  */
-/* USER CODE END Header_StartDefaultTask */
-void StartDefaultTask(void *argument)
-{
-  /* USER CODE BEGIN StartDefaultTask */
-  (void)argument;
-  
-  /* Infinite loop - LED heartbeat */
-  for(;;)
-  {
-    /* Toggle LED (PC13, active low) */
-    HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
-    
-    /* 500ms toggle = 1Hz blink rate */
-    osDelay(500);
-  }
-  /* USER CODE END StartDefaultTask */
-}
-
-/* Private application code --------------------------------------------------*/
-/* USER CODE BEGIN Application */
-
-/**
- * @brief LwIP task - handles network stack initialization and processing
- */
-void LwIPTask(void *argument)
-{
-    (void)argument;
-    
-    ip4_addr_t ipaddr, netmask, gw;
-    uart_config_t uart_server_cfg;
-    uart_config_t uart_client_cfg;
-    uint8_t use_dhcp = 0;
-    const device_config_t *cfg;
-    
-    /* Wait for configuration to be loaded */
-    vTaskDelay(pdMS_TO_TICKS(100));
-    
-    /* Get device configuration */
-    cfg = config_get();
-    
-    /* Initialize UART transparent transmission module */
-    uart_trans_init();
-
-    /* Apply UART settings from configuration */
-    uart_server_cfg.baudrate = UART_DEFAULT_BAUDRATE;
-    uart_server_cfg.data_bits = UART_DEFAULT_DATA_BITS;
-    uart_server_cfg.stop_bits = UART_DEFAULT_STOP_BITS;
-    uart_server_cfg.parity = UART_DEFAULT_PARITY;
-
-    uart_client_cfg.baudrate = UART_DEFAULT_BAUDRATE;
-    uart_client_cfg.data_bits = UART_DEFAULT_DATA_BITS;
-    uart_client_cfg.stop_bits = UART_DEFAULT_STOP_BITS;
-    uart_client_cfg.parity = UART_DEFAULT_PARITY;
-
-    if (cfg != NULL)
-    {
-        uart_server_cfg.baudrate = cfg->uart2_baudrate;
-        uart_server_cfg.data_bits = cfg->uart2_databits;
-        uart_server_cfg.stop_bits = cfg->uart2_stopbits;
-        uart_server_cfg.parity = cfg->uart2_parity;
-
-        uart_client_cfg.baudrate = cfg->uart3_baudrate;
-        uart_client_cfg.data_bits = cfg->uart3_databits;
-        uart_client_cfg.stop_bits = cfg->uart3_stopbits;
-        uart_client_cfg.parity = cfg->uart3_parity;
-    }
-
-    (void)uart_trans_config(UART_CHANNEL_SERVER, &uart_server_cfg);
-    (void)uart_trans_config(UART_CHANNEL_CLIENT, &uart_client_cfg);
-    
-    /* Wait for TCP tasks to initialize their StreamBuffers */
-    /* TCP Server and TCP Client tasks call tcp_server_init() / tcp_client_init() */
-    /* which create the StreamBuffers. We need to wait until they're ready. */
-    while (tcp_server_get_rx_stream() == NULL ||
-           tcp_server_get_tx_stream() == NULL ||
-           tcp_client_get_rx_stream() == NULL ||
-           tcp_client_get_tx_stream() == NULL)
-    {
-        vTaskDelay(pdMS_TO_TICKS(50));
-    }
-    
-    /* Connect StreamBuffers between TCP and UART modules */
-    /* Server: TCP Server RX -> UART2 TX, UART2 RX -> TCP Server TX */
-    uart_trans_set_streams(UART_CHANNEL_SERVER,
-                           tcp_server_get_rx_stream(),  /* TCP RX -> UART TX */
-                           tcp_server_get_tx_stream()); /* UART RX -> TCP TX */
-    
-    /* Client: TCP Client RX -> UART3 TX, UART3 RX -> TCP Client TX */
-    uart_trans_set_streams(UART_CHANNEL_CLIENT,
-                           tcp_client_get_rx_stream(),  /* TCP RX -> UART TX */
-                           tcp_client_get_tx_stream()); /* UART RX -> TCP TX */
-    
-    /* Initialize LwIP stack (calls tcpip_init internally) */
-    tcpip_init(NULL, NULL);
-    
-    /* Wait for tcpip thread to initialize */
-    vTaskDelay(pdMS_TO_TICKS(100));
-    
-    /* Set IP addresses */
-    if (cfg != NULL && cfg->dhcp_enable != 0)
-    {
-        use_dhcp = 1;
-        IP4_ADDR(&ipaddr, 0, 0, 0, 0);
-        IP4_ADDR(&netmask, 0, 0, 0, 0);
-        IP4_ADDR(&gw, 0, 0, 0, 0);
-    }
-    else if (cfg != NULL)
-    {
-        IP4_ADDR(&ipaddr, cfg->ip[0], cfg->ip[1], cfg->ip[2], cfg->ip[3]);
-        IP4_ADDR(&netmask, cfg->mask[0], cfg->mask[1], cfg->mask[2], cfg->mask[3]);
-        IP4_ADDR(&gw, cfg->gw[0], cfg->gw[1], cfg->gw[2], cfg->gw[3]);
-    }
-    else
-    {
-        /* Default IP if no config */
-        IP4_ADDR(&ipaddr, 192, 168, 1, 200);
-        IP4_ADDR(&netmask, 255, 255, 255, 0);
-        IP4_ADDR(&gw, 192, 168, 1, 1);
-    }
-    
-    /* Initialize network interface */
-    lwip_netif_init(&ipaddr, &netmask, &gw);
-
-    if (use_dhcp)
-    {
-        dhcp_start(&ch390_netif);
-    }
-    
-    /* Main loop - handle network events */
-    for (;;)
-    {
-        /* Wait for CH390 interrupt or timeout */
-        if (xSemaphoreTake(ch390IntSemaphore, pdMS_TO_TICKS(10)) == pdTRUE)
-        {
-            /* Process network input - poll all pending packets */
-            ethernetif_poll();
-        }
-        
-        /* Check link status periodically */
-        ethernetif_check_link();
-    }
-}
-
-/**
- * @brief Get SPI mutex handle for CH390 driver
- */
-SemaphoreHandle_t get_ch390_spi_mutex(void)
-{
-    return ch390SpiMutex;
-}
-
-/**
- * @brief Notify LwIP task of CH390 interrupt (call from ISR)
- */
-void notify_ch390_interrupt_from_isr(void)
-{
-    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
-    
-    if (ch390IntSemaphore != NULL)
-    {
-        xSemaphoreGiveFromISR(ch390IntSemaphore, &xHigherPriorityTaskWoken);
-        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
-    }
-}
-
-/**
- * @brief Get UART Server transparent task handle
- */
-TaskHandle_t get_uart_server_task_handle(void)
-{
-    return uartServerTransTaskHandle;
-}
-
-/**
- * @brief Get UART Client transparent task handle
- */
-TaskHandle_t get_uart_client_task_handle(void)
-{
-    return uartClientTransTaskHandle;
-}
-
-/* USER CODE END Application */

Core/Src/gpio.c

@@ -56,6 +56,9 @@ void MX_GPIO_Init(void)
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1, GPIO_PIN_RESET);
 
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_SET);
+
   /*Configure GPIO pin : PC13 */
   GPIO_InitStruct.Pin = GPIO_PIN_13;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@@ -65,7 +68,7 @@ void MX_GPIO_Init(void)
 
   /*Configure GPIO pin : PB0 */
   GPIO_InitStruct.Pin = GPIO_PIN_0;
-  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
@@ -76,6 +79,17 @@ void MX_GPIO_Init(void)
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
+  /*Configure GPIO pin : PA4 */
+  GPIO_InitStruct.Pin = GPIO_PIN_4;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  HAL_NVIC_SetPriority(EXTI0_IRQn, 6, 0);
+  HAL_NVIC_EnableIRQ(EXTI0_IRQn);
+
 }
 
 /* USER CODE BEGIN 2 */

Core/Src/main.c

@@ -4,194 +4,507 @@
   * @file           : main.c
   * @brief          : Main program body
   ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2026 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
   */
 /* USER CODE END Header */
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
-#include "cmsis_os.h"
 #include "dma.h"
 #include "iwdg.h"
 #include "spi.h"
+#include "tim.h"
 #include "usart.h"
 #include "gpio.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
 #include <stdio.h>
+#include <string.h>
 
 #include "CH390.h"
+#include "CH390_Interface.h"
+#include "SEGGER_RTT.h"
 #include "config.h"
-#include "flash_param.h"
+#include "ethernetif.h"
+#include "ch390_runtime.h"
+#include "lwip/init.h"
+#include "lwip/timeouts.h"
+#include "tcp_client.h"
+#include "tcp_server.h"
 #include "uart_trans.h"
 /* USER CODE END Includes */
 
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN PTD */
-
-/* USER CODE END PTD */
-
 /* Private define ------------------------------------------------------------*/
 /* USER CODE BEGIN PD */
-/* CH390 硬件控制引脚 */
-#define CH390_RST_PIN       GPIO_PIN_1
-#define CH390_RST_PORT      GPIOB
-#define CH390_CS_PIN        GPIO_PIN_4
-#define CH390_CS_PORT       GPIOA
-
-/* LED 指示灯 */
 #define LED_PIN             GPIO_PIN_13
 #define LED_PORT            GPIOC
+#define APP_ROUTE_BUFFER_SIZE 256u
+#define STACK_GUARD_WORD     0xA5A5A5A5u
+#define APP_HEALTH_CHECK_INTERVAL_MS 5000u
 /* USER CODE END PD */
 
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN PM */
-
-/* USER CODE END PM */
-
 /* Private variables ---------------------------------------------------------*/
-
 /* USER CODE BEGIN PV */
-
+static volatile uint16_t g_led_blink_ticks = 0;
+static uint8_t g_clock_fallback_to_hsi = 0u;
+volatile uint8_t g_uart1_rx_probe_byte = 0u;
+static uint8_t g_stack_guard_reported = 0u;
+static uint8_t g_mux_response_frame[272];
+static uint8_t g_links_started = 0u;
 /* USER CODE END PV */
 
 /* Private function prototypes -----------------------------------------------*/
 void SystemClock_Config(void);
-void MX_FREERTOS_Init(void);
 /* USER CODE BEGIN PFP */
-static void CH390_HardwareReset(void);
 static void LED_Init(void);
+static void LED_StartBlink(void);
+static void BootDiag_ReportCh390(void);
+static void App_Init(void);
+static void App_Poll(void);
+static void App_ConfigureLinks(const device_config_t *cfg);
+static void App_RouteRawUartTraffic(void);
+static void App_RouteMuxUartTraffic(void);
+static void App_RouteTcpTraffic(void);
+static void StackGuard_Init(void);
+static void StackGuard_Check(void);
+static void App_SendToUart(uint8_t uart_index, uint8_t src_id, uint8_t dst_mask, const uint8_t *data, uint16_t len);
 /* USER CODE END PFP */
 
 /* Private user code ---------------------------------------------------------*/
 /* USER CODE BEGIN 0 */
+extern uint32_t Stack_Mem[];
 
-/**
- * @brief CH390 硬件复位
- * @note  复位时序: RST 低电平至少 10us，然后高电平等待 50ms 完成初始化
- */
-static void CH390_HardwareReset(void)
-{
-    /* 拉低 RST 引脚 */
-    HAL_GPIO_WritePin(CH390_RST_PORT, CH390_RST_PIN, GPIO_PIN_RESET);
-    HAL_Delay(1);  /* 保持低电平 1ms (远超最小 10us 要求) */
-    
-    /* 拉高 RST 引脚，等待芯片初始化完成 */
-    HAL_GPIO_WritePin(CH390_RST_PORT, CH390_RST_PIN, GPIO_PIN_SET);
-    HAL_Delay(50); /* 等待 50ms */
-    
-    /* 确保 CS 为高电平（未选中状态） */
-    HAL_GPIO_WritePin(CH390_CS_PORT, CH390_CS_PIN, GPIO_PIN_SET);
-}
-
-/**
- * @brief LED 初始化（点亮表示系统启动）
- */
 static void LED_Init(void)
 {
-    /* LED 灭（PC13 高电平灭，低电平亮） */
     HAL_GPIO_WritePin(LED_PORT, LED_PIN, GPIO_PIN_SET);
 }
 
-/**
- * @brief LED 闪烁（用于指示系统运行状态）
- */
+static void StackGuard_Init(void)
+{
+    Stack_Mem[0] = STACK_GUARD_WORD;
+    g_stack_guard_reported = 0u;
+}
+
+static void StackGuard_Check(void)
+{
+    if (Stack_Mem[0] != STACK_GUARD_WORD) {
+        if (g_stack_guard_reported == 0u) {
+            g_stack_guard_reported = 1u;
+            SEGGER_RTT_WriteString(0, "ERROR: Main stack guard overwritten\r\n");
+        }
+        __disable_irq();
+        NVIC_SystemReset();
+    }
+}
+
+static void LED_StartBlink(void)
+{
+    if (HAL_TIM_Base_Start_IT(&htim4) != HAL_OK) {
+        Error_Handler();
+    }
+}
+
 void LED_Toggle(void)
 {
     HAL_GPIO_TogglePin(LED_PORT, LED_PIN);
 }
 
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+    if (htim->Instance == TIM4) {
+        g_led_blink_ticks++;
+        if (g_led_blink_ticks >= 1000u) {
+            g_led_blink_ticks = 0u;
+            LED_Toggle();
+        }
+    }
+}
+
+static void BootDiag_ReportCh390(void)
+{
+    ch390_diag_t diag;
+    const device_config_t *cfg = config_get();
+    uint8_t mac_hw[6];
+
+    ch390_runtime_get_diag(&diag);
+    ch390_get_mac(mac_hw);
+
+    SEGGER_RTT_printf(0,
+                      "CH390 VID=0x%04X PID=0x%04X REV=0x%02X LINK=%u MAC=%02X:%02X:%02X:%02X:%02X:%02X\r\n",
+                      diag.vendor_id,
+                      diag.product_id,
+                      diag.revision,
+                      diag.link_up,
+                      mac_hw[0], mac_hw[1], mac_hw[2], mac_hw[3], mac_hw[4], mac_hw[5]);
+    SEGGER_RTT_printf(0,
+                      "NET cfg IP=%u.%u.%u.%u MASK=%u.%u.%u.%u GW=%u.%u.%u.%u MUX=%u\r\n",
+                      cfg->net.ip[0], cfg->net.ip[1], cfg->net.ip[2], cfg->net.ip[3],
+                      cfg->net.mask[0], cfg->net.mask[1], cfg->net.mask[2], cfg->net.mask[3],
+                      cfg->net.gw[0], cfg->net.gw[1], cfg->net.gw[2], cfg->net.gw[3],
+                      cfg->mux_mode);
+}
+
+static void App_ConfigureLinks(const device_config_t *cfg)
+{
+    tcp_server_instance_config_t server_cfg;
+    tcp_client_instance_config_t client_cfg;
+
+    (void)tcp_server_init_all();
+    (void)tcp_client_init_all();
+
+    server_cfg.enabled = (cfg->links[CONFIG_LINK_S1].enabled != 0u);
+    server_cfg.port = cfg->links[CONFIG_LINK_S1].local_port;
+    (void)tcp_server_config(0u, &server_cfg);
+
+    server_cfg.enabled = (cfg->links[CONFIG_LINK_S2].enabled != 0u);
+    server_cfg.port = cfg->links[CONFIG_LINK_S2].local_port;
+    (void)tcp_server_config(1u, &server_cfg);
+
+    memcpy(client_cfg.remote_ip, cfg->links[CONFIG_LINK_C1].remote_ip, sizeof(client_cfg.remote_ip));
+    client_cfg.local_port = cfg->links[CONFIG_LINK_C1].local_port;
+    client_cfg.remote_port = cfg->links[CONFIG_LINK_C1].remote_port;
+    client_cfg.reconnect_interval_ms = TCP_CLIENT_RECONNECT_DELAY_MS;
+    client_cfg.enabled = (cfg->links[CONFIG_LINK_C1].enabled != 0u);
+    client_cfg.auto_reconnect = true;
+    (void)tcp_client_config(0u, &client_cfg);
+
+    memcpy(client_cfg.remote_ip, cfg->links[CONFIG_LINK_C2].remote_ip, sizeof(client_cfg.remote_ip));
+    client_cfg.local_port = cfg->links[CONFIG_LINK_C2].local_port;
+    client_cfg.remote_port = cfg->links[CONFIG_LINK_C2].remote_port;
+    client_cfg.enabled = (cfg->links[CONFIG_LINK_C2].enabled != 0u);
+    (void)tcp_client_config(1u, &client_cfg);
+}
+
+static void App_StartLinksIfNeeded(void)
+{
+    int any_failed;
+
+    if ((g_links_started != 0u) || !netif_is_link_up(&ch390_netif)) {
+        return;
+    }
+
+    any_failed = 0;
+    for (uint8_t i = 0; i < TCP_SERVER_INSTANCE_COUNT; ++i) {
+        if (tcp_server_start(i) != 0) {
+            any_failed = 1;
+        }
+    }
+    for (uint8_t i = 0; i < TCP_CLIENT_INSTANCE_COUNT; ++i) {
+        if (tcp_client_connect(i) != 0) {
+            any_failed = 1;
+        }
+    }
+
+    if (any_failed) {
+        SEGGER_RTT_WriteString(0, "NET links start partially failed, will retry\r\n");
+        return;
+    }
+
+    g_links_started = 1u;
+    SEGGER_RTT_WriteString(0, "NET links started after link-up\r\n");
+}
+
+static void App_StopLinksIfNeeded(void)
+{
+    if (netif_is_link_up(&ch390_netif)) {
+        return;
+    }
+
+    if (g_links_started != 0u) {
+        for (uint8_t i = 0; i < TCP_CLIENT_INSTANCE_COUNT; ++i) {
+            (void)tcp_client_disconnect(i);
+        }
+        for (uint8_t i = 0; i < TCP_SERVER_INSTANCE_COUNT; ++i) {
+            (void)tcp_server_stop(i);
+        }
+        SEGGER_RTT_WriteString(0, "NET links stopped after link-down\r\n");
+    }
+
+    g_links_started = 0u;
+}
+
+static void App_Init(void)
+{
+    const device_config_t *cfg;
+    ip4_addr_t ipaddr;
+    ip4_addr_t netmask;
+    ip4_addr_t gateway;
+    uart_config_t uart_cfg;
+
+    (void)config_init();
+    cfg = config_get();
+
+    (void)uart_trans_init();
+    uart_cfg.baudrate = cfg->uart_baudrate[0];
+    (void)uart_trans_config(UART_CHANNEL_U0, &uart_cfg);
+    uart_cfg.baudrate = cfg->uart_baudrate[1];
+    (void)uart_trans_config(UART_CHANNEL_U1, &uart_cfg);
+    (void)uart_trans_start(UART_CHANNEL_U0);
+    (void)uart_trans_start(UART_CHANNEL_U1);
+
+    SEGGER_RTT_Init();
+    StackGuard_Init();
+    SEGGER_RTT_WriteString(0, "\r\nTCP2UART boot\r\n");
+    if (g_clock_fallback_to_hsi != 0u) {
+        SEGGER_RTT_WriteString(0, "WARN: HSE start failed, fallback to HSI PLL\r\n");
+    }
+
+    lwip_init();
+    IP4_ADDR(&ipaddr, cfg->net.ip[0], cfg->net.ip[1], cfg->net.ip[2], cfg->net.ip[3]);
+    IP4_ADDR(&netmask, cfg->net.mask[0], cfg->net.mask[1], cfg->net.mask[2], cfg->net.mask[3]);
+    IP4_ADDR(&gateway, cfg->net.gw[0], cfg->net.gw[1], cfg->net.gw[2], cfg->net.gw[3]);
+    lwip_netif_init(&ipaddr, &netmask, &gateway);
+    App_ConfigureLinks(cfg);
+    BootDiag_ReportCh390();
+
+    if (HAL_UART_Receive_IT(&huart1, (uint8_t *)&g_uart1_rx_probe_byte, 1u) != HAL_OK) {
+        Error_Handler();
+    }
+}
+
+static void App_SendToUart(uint8_t uart_index, uint8_t src_id, uint8_t dst_mask, const uint8_t *data, uint16_t len)
+{
+    const device_config_t *cfg = config_get();
+    uart_channel_t channel = (uart_index == LINK_UART_U1) ? UART_CHANNEL_U1 : UART_CHANNEL_U0;
+
+    if (cfg->mux_mode == MUX_MODE_FRAME) {
+        uint8_t frame[APP_ROUTE_BUFFER_SIZE + 6u];
+        uint16_t frame_len = 0u;
+        if (uart_mux_encode_frame(src_id, dst_mask, data, len, frame, &frame_len, sizeof(frame))) {
+            (void)uart_trans_write(channel, frame, frame_len);
+        }
+    } else {
+        (void)uart_trans_write(channel, data, len);
+    }
+}
+
+static void App_RouteTcpTraffic(void)
+{
+    const device_config_t *cfg = config_get();
+    uint8_t buffer[APP_ROUTE_BUFFER_SIZE];
+
+    for (uint8_t i = 0; i < TCP_SERVER_INSTANCE_COUNT; ++i) {
+        int rc = tcp_server_recv(i, buffer, sizeof(buffer));
+        if (rc > 0) {
+            uint8_t link_index = (i == 0u) ? CONFIG_LINK_S1 : CONFIG_LINK_S2;
+            App_SendToUart(cfg->links[link_index].uart,
+                           config_link_index_to_endpoint(link_index),
+                           config_uart_index_to_endpoint(cfg->links[link_index].uart),
+                           buffer,
+                           (uint16_t)rc);
+        }
+    }
+
+    for (uint8_t i = 0; i < TCP_CLIENT_INSTANCE_COUNT; ++i) {
+        int rc = tcp_client_recv(i, buffer, sizeof(buffer));
+        if (rc > 0) {
+            uint8_t link_index = (i == 0u) ? CONFIG_LINK_C1 : CONFIG_LINK_C2;
+            App_SendToUart(cfg->links[link_index].uart,
+                           config_link_index_to_endpoint(link_index),
+                           config_uart_index_to_endpoint(cfg->links[link_index].uart),
+                           buffer,
+                           (uint16_t)rc);
+        }
+    }
+}
+
+static void App_RouteRawUartTraffic(void)
+{
+    const device_config_t *cfg = config_get();
+    uint8_t buffer[APP_ROUTE_BUFFER_SIZE];
+    uint16_t len;
+
+    len = uart_trans_read(UART_CHANNEL_U0, buffer, sizeof(buffer));
+    if (len > 0u) {
+        for (uint8_t i = 0; i < CONFIG_LINK_COUNT; ++i) {
+            if (cfg->links[i].enabled == 0u || cfg->links[i].uart != LINK_UART_U0) {
+                continue;
+            }
+            if (i == CONFIG_LINK_S1) {
+                (void)tcp_server_send(0u, buffer, len);
+            } else if (i == CONFIG_LINK_S2) {
+                (void)tcp_server_send(1u, buffer, len);
+            } else if (i == CONFIG_LINK_C1) {
+                (void)tcp_client_send(0u, buffer, len);
+            } else if (i == CONFIG_LINK_C2) {
+                (void)tcp_client_send(1u, buffer, len);
+            }
+        }
+    }
+
+    len = uart_trans_read(UART_CHANNEL_U1, buffer, sizeof(buffer));
+    if (len > 0u) {
+        for (uint8_t i = 0; i < CONFIG_LINK_COUNT; ++i) {
+            if (cfg->links[i].enabled == 0u || cfg->links[i].uart != LINK_UART_U1) {
+                continue;
+            }
+            if (i == CONFIG_LINK_S1) {
+                (void)tcp_server_send(0u, buffer, len);
+            } else if (i == CONFIG_LINK_S2) {
+                (void)tcp_server_send(1u, buffer, len);
+            } else if (i == CONFIG_LINK_C1) {
+                (void)tcp_client_send(0u, buffer, len);
+            } else if (i == CONFIG_LINK_C2) {
+                (void)tcp_client_send(1u, buffer, len);
+            }
+        }
+    }
+}
+
+static void App_RouteMuxUartTraffic(void)
+{
+    uart_mux_frame_t frame;
+    const device_config_t *cfg = config_get();
+
+    while (uart_mux_try_extract_frame(UART_CHANNEL_U0, &frame)) {
+#if defined(DEBUG) && (DEBUG != 0)
+        SEGGER_RTT_printf(0, "Mux frame from UART0: src_id=%u dst_mask=0x%02X len=%u\r\n", frame.src_id, frame.dst_mask, frame.payload_len);
+#endif
+        if (frame.dst_mask == 0u) {
+            at_result_t result;
+            char *response_text = (char *)&g_mux_response_frame[5];
+            if (config_build_response_frame(frame.payload, frame.payload_len, response_text, (uint16_t)(sizeof(g_mux_response_frame) - 6u), &result)) {
+                uint16_t response_len = (uint16_t)strlen(response_text);
+                uint16_t frame_len = 0u;
+                if (uart_mux_encode_frame(config_uart_index_to_endpoint(LINK_UART_U0), 0u, (const uint8_t *)response_text, response_len, g_mux_response_frame, &frame_len, sizeof(g_mux_response_frame))) {
+                    (void)uart_trans_write(UART_CHANNEL_U0, g_mux_response_frame, frame_len);
+                }
+                if (result == AT_NEED_REBOOT) {
+                    static const char hint[] = "Note: Use AT+SAVE then AT+RESET to apply changes\r\n";
+                    response_len = (uint16_t)strlen(hint);
+                    if (uart_mux_encode_frame(config_uart_index_to_endpoint(LINK_UART_U0), 0u, (const uint8_t *)hint, response_len, g_mux_response_frame, &frame_len, sizeof(g_mux_response_frame))) {
+                        (void)uart_trans_write(UART_CHANNEL_U0, g_mux_response_frame, frame_len);
+                    }
+                }
+            }
+            continue;
+        }
+
+        if ((frame.dst_mask & ENDPOINT_S1) != 0u) {
+            (void)tcp_server_send(0u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_S2) != 0u) {
+            (void)tcp_server_send(1u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_C1) != 0u) {
+            (void)tcp_client_send(0u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_C2) != 0u) {
+            (void)tcp_client_send(1u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_UART3) != 0u && cfg->links[CONFIG_LINK_S2].uart == LINK_UART_U1) {
+            App_SendToUart(LINK_UART_U1, frame.src_id, ENDPOINT_UART3, frame.payload, frame.payload_len);
+        }
+    }
+
+    while (uart_mux_try_extract_frame(UART_CHANNEL_U1, &frame)) {
+#if defined(DEBUG) && (DEBUG != 0)
+        SEGGER_RTT_printf(0, "Mux frame from UART1: src_id=%u dst_mask=0x%02X len=%u\r\n", frame.src_id, frame.dst_mask, frame.payload_len);
+#endif
+        if (frame.dst_mask == 0u) {
+            at_result_t result;
+            char *response_text = (char *)&g_mux_response_frame[5];
+            if (config_build_response_frame(frame.payload, frame.payload_len, response_text, (uint16_t)(sizeof(g_mux_response_frame) - 6u), &result)) {
+                uint16_t response_len = (uint16_t)strlen(response_text);
+                uint16_t frame_len = 0u;
+                if (uart_mux_encode_frame(config_uart_index_to_endpoint(LINK_UART_U1), 0u, (const uint8_t *)response_text, response_len, g_mux_response_frame, &frame_len, sizeof(g_mux_response_frame))) {
+                    (void)uart_trans_write(UART_CHANNEL_U1, g_mux_response_frame, frame_len);
+                }
+                if (result == AT_NEED_REBOOT) {
+                    static const char hint[] = "Note: Use AT+SAVE then AT+RESET to apply changes\r\n";
+                    response_len = (uint16_t)strlen(hint);
+                    if (uart_mux_encode_frame(config_uart_index_to_endpoint(LINK_UART_U1), 0u, (const uint8_t *)hint, response_len, g_mux_response_frame, &frame_len, sizeof(g_mux_response_frame))) {
+                        (void)uart_trans_write(UART_CHANNEL_U1, g_mux_response_frame, frame_len);
+                    }
+                }
+            }
+            continue;
+        }
+
+        if ((frame.dst_mask & ENDPOINT_S1) != 0u) {
+            (void)tcp_server_send(0u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_S2) != 0u) {
+            (void)tcp_server_send(1u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_C1) != 0u) {
+            (void)tcp_client_send(0u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_C2) != 0u) {
+            (void)tcp_client_send(1u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_UART2) != 0u) {
+            App_SendToUart(LINK_UART_U0, frame.src_id, ENDPOINT_UART2, frame.payload, frame.payload_len);
+        }
+    }
+}
+
+static void App_Poll(void)
+{
+    static uint32_t s_health_check_tick;
+    uint32_t now;
+
+    ethernetif_poll();
+    ethernetif_check_link();
+    sys_check_timeouts();
+    App_StopLinksIfNeeded();
+    App_StartLinksIfNeeded();
+    tcp_client_poll();
+    uart_trans_poll();
+    StackGuard_Check();
+    config_poll();
+    App_RouteTcpTraffic();
+
+    if (config_get()->mux_mode == MUX_MODE_FRAME) {
+        App_RouteMuxUartTraffic();
+    } else {
+        App_RouteRawUartTraffic();
+    }
+
+    now = HAL_GetTick();
+    if ((now - s_health_check_tick) >= APP_HEALTH_CHECK_INTERVAL_MS) {
+        s_health_check_tick = now;
+        ch390_runtime_health_check(&ch390_netif);
+    }
+
+    if (config_is_reset_requested()) {
+        config_clear_reset_requested();
+        NVIC_SystemReset();
+    }
+
+    if (hiwdg.Instance == IWDG) {
+        HAL_IWDG_Refresh(&hiwdg);
+    }
+}
 /* USER CODE END 0 */
 
-/**
-  * @brief  The application entry point.
-  * @retval int
-  */
 int main(void)
 {
-
-  /* USER CODE BEGIN 1 */
-
-  /* USER CODE END 1 */
-
-  /* MCU Configuration--------------------------------------------------------*/
-
-  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
   HAL_Init();
-
-  /* USER CODE BEGIN Init */
-
-  /* USER CODE END Init */
-
-  /* Configure the system clock */
   SystemClock_Config();
-
-  /* USER CODE BEGIN SysInit */
-
-  /* USER CODE END SysInit */
-
-  /* Initialize all configured peripherals */
   MX_GPIO_Init();
   MX_DMA_Init();
-  MX_IWDG_Init();
   MX_USART1_UART_Init();
   MX_USART2_UART_Init();
   MX_USART3_UART_Init();
   MX_SPI1_Init();
-  /* USER CODE BEGIN 2 */
+  MX_TIM4_Init();
 
-  /* LED 初始化 */
   LED_Init();
+  LED_StartBlink();
+  App_Init();
 
-  /* CH390 硬件复位 */
-  CH390_HardwareReset();
-  
-  /* Initialize configuration from Flash (fallback to defaults on invalid data) */
-  config_init();
-  
-  /* USER CODE END 2 */
-
-  /* Init scheduler */
-  osKernelInitialize();  /* Call init function for freertos objects (in cmsis_os2.c) */
-  MX_FREERTOS_Init();
-
-  /* Start scheduler */
-  osKernelStart();
-
-  /* We should never get here as control is now taken by the scheduler */
-
-  /* Infinite loop */
-  /* USER CODE BEGIN WHILE */
   while (1)
   {
-    /* USER CODE END WHILE */
-
-    /* USER CODE BEGIN 3 */
+    App_Poll();
   }
-  /* USER CODE END 3 */
 }
 
-/**
-  * @brief System Clock Configuration
-  * @retval None
-  */
 void SystemClock_Config(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Initializes the RCC Oscillators according to the specified parameters
-  * in the RCC_OscInitTypeDef structure.
-  */
+  g_clock_fallback_to_hsi = 0u;
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
   RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
@@ -200,13 +513,20 @@ void SystemClock_Config(void)
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
   RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    Error_Handler();
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+    RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+      Error_Handler();
+    }
+    g_clock_fallback_to_hsi = 1u;
   }
 
-  /** Initializes the CPU, AHB and APB buses clocks
-  */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -220,54 +540,43 @@ void SystemClock_Config(void)
   }
 }
 
-/* USER CODE BEGIN 4 */
-
-/**
- * @brief  重定向 printf 到 UART1（调试输出）
- */
 #ifdef __GNUC__
 int _write(int file, char *ptr, int len)
 {
-    HAL_UART_Transmit(&huart1, (uint8_t *)ptr, len, HAL_MAX_DELAY);
-    return len;
+    (void)file;
+    return (int)SEGGER_RTT_Write(0, ptr, (unsigned)len);
 }
 #else
 int fputc(int ch, FILE *f)
 {
-    HAL_UART_Transmit(&huart1, (uint8_t *)&ch, 1, HAL_MAX_DELAY);
+    (void)f;
+    SEGGER_RTT_PutChar(0, (char)ch);
     return ch;
 }
 #endif
 
-/* USER CODE END 4 */
+void Debug_TrapWithRttHint(const char *tag)
+{
+    SEGGER_RTT_WriteString(0, "\r\nTRAP: ");
+    SEGGER_RTT_WriteString(0, tag);
+    SEGGER_RTT_WriteString(0, "\r\n");
+    __disable_irq();
+    __BKPT(0);
+    while (1)
+    {
+    }
+}
 
-/**
-  * @brief  This function is executed in case of error occurrence.
-  * @retval None
-  */
 void Error_Handler(void)
 {
-  /* USER CODE BEGIN Error_Handler_Debug */
-  /* User can add his own implementation to report the HAL error return state */
-  __disable_irq();
-  while (1)
-  {
-  }
-  /* USER CODE END Error_Handler_Debug */
+  Debug_TrapWithRttHint("Error_Handler");
 }
+
 #ifdef USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
 void assert_failed(uint8_t *file, uint32_t line)
 {
-  /* USER CODE BEGIN 6 */
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-  /* USER CODE END 6 */
+  (void)file;
+  (void)line;
+  Debug_TrapWithRttHint("assert_failed");
 }
-#endif /* USE_FULL_ASSERT */
+#endif

Core/Src/spi.c

@@ -41,10 +41,10 @@ void MX_SPI1_Init(void)
   hspi1.Init.Mode = SPI_MODE_MASTER;
   hspi1.Init.Direction = SPI_DIRECTION_2LINES;
   hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
-  hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;   /* CH390 requires CPOL=High (Mode 3) */
-  hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;        /* CH390 requires CPHA=2Edge (Mode 3) */
+  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;    /* Match CH390 runtime baseline: CPOL=Low */
+  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;        /* Match CH390 runtime baseline: CPHA=1Edge (Mode 0) */
   hspi1.Init.NSS = SPI_NSS_SOFT;                /* Software CS control for CH390 */
-  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; /* 72MHz/8 = 9MHz (CH390 max 10MHz) */
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; /* 72MHz/2 = 36MHz, max SPI1 clock at current APB2 */
   hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
   hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
   hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@@ -73,7 +73,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
 
     __HAL_RCC_GPIOA_CLK_ENABLE();
     /**SPI1 GPIO Configuration
-    PA4     ------> CH390 CS (GPIO Output, controlled by CH390_Interface.c)
+    PA4     ------> GPIO_Output
     PA5     ------> SPI1_SCK
     PA6     ------> SPI1_MISO
     PA7     ------> SPI1_MOSI
@@ -90,7 +90,11 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
     GPIO_InitStruct.Pull = GPIO_NOPULL;
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
     
-    /* PA4 (CS) is configured as GPIO output in CH390_Interface.c */
+    GPIO_InitStruct.Pin = GPIO_PIN_4;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
     /* SPI1 interrupt Init */
     HAL_NVIC_SetPriority(SPI1_IRQn, 5, 0);
@@ -113,12 +117,12 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
     __HAL_RCC_SPI1_CLK_DISABLE();
 
     /**SPI1 GPIO Configuration
-    PA4     ------> CH390 CS (handled by CH390_Interface.c)
+    PA4     ------> GPIO_Output
     PA5     ------> SPI1_SCK
     PA6     ------> SPI1_MISO
     PA7     ------> SPI1_MOSI
     */
-    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
 
     /* SPI1 interrupt Deinit */
     HAL_NVIC_DisableIRQ(SPI1_IRQn);

Core/Src/stm32f1xx_hal_msp.c

@@ -71,8 +71,6 @@ void HAL_MspInit(void)
   __HAL_RCC_PWR_CLK_ENABLE();
 
   /* System interrupt init*/
-  /* PendSV_IRQn interrupt configuration */
-  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
 
   /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
   */

Core/Src/stm32f1xx_it.c

@@ -4,65 +4,17 @@
   * @file    stm32f1xx_it.c
   * @brief   Interrupt Service Routines.
   ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2026 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
   */
 /* USER CODE END Header */
 
-/* Includes ------------------------------------------------------------------*/
 #include "main.h"
 #include "stm32f1xx_it.h"
-#include "FreeRTOS.h"
-#include "task.h"
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
+#include "ethernetif.h"
 #include "uart_trans.h"
 #include "config.h"
 
-/* External functions from freertos.c */
-extern void notify_ch390_interrupt_from_isr(void);
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN TD */
-
-/* USER CODE END TD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN PD */
-
-/* USER CODE END PD */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN PM */
-
-/* USER CODE END PM */
-
-/* Private variables ---------------------------------------------------------*/
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* Private user code ---------------------------------------------------------*/
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-
-/* External variables --------------------------------------------------------*/
 extern SPI_HandleTypeDef hspi1;
+extern TIM_HandleTypeDef htim4;
 extern DMA_HandleTypeDef hdma_usart1_rx;
 extern DMA_HandleTypeDef hdma_usart1_tx;
 extern DMA_HandleTypeDef hdma_usart2_rx;
@@ -72,343 +24,153 @@ extern DMA_HandleTypeDef hdma_usart3_tx;
 extern UART_HandleTypeDef huart1;
 extern UART_HandleTypeDef huart2;
 extern UART_HandleTypeDef huart3;
-/* USER CODE BEGIN EV */
+extern volatile uint8_t g_uart1_rx_probe_byte;
 
-/* USER CODE END EV */
-
-/******************************************************************************/
-/*           Cortex-M3 Processor Interruption and Exception Handlers          */
-/******************************************************************************/
-/**
-  * @brief This function handles Non maskable interrupt.
-  */
 void NMI_Handler(void)
 {
-  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
-
-  /* USER CODE END NonMaskableInt_IRQn 0 */
-  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-   while (1)
-  {
-  }
-  /* USER CODE END NonMaskableInt_IRQn 1 */
+  Debug_TrapWithRttHint("NMI_Handler");
 }
 
-/**
-  * @brief This function handles Hard fault interrupt.
-  */
 void HardFault_Handler(void)
 {
-  /* USER CODE BEGIN HardFault_IRQn 0 */
-
-  /* USER CODE END HardFault_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
-    /* USER CODE END W1_HardFault_IRQn 0 */
-  }
+  Debug_TrapWithRttHint("HardFault_Handler");
 }
 
-/**
-  * @brief This function handles Memory management fault.
-  */
 void MemManage_Handler(void)
 {
-  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
-  /* USER CODE END MemoryManagement_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
-    /* USER CODE END W1_MemoryManagement_IRQn 0 */
-  }
+  Debug_TrapWithRttHint("MemManage_Handler");
 }
 
-/**
-  * @brief This function handles Prefetch fault, memory access fault.
-  */
 void BusFault_Handler(void)
 {
-  /* USER CODE BEGIN BusFault_IRQn 0 */
-
-  /* USER CODE END BusFault_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
-    /* USER CODE END W1_BusFault_IRQn 0 */
-  }
+  Debug_TrapWithRttHint("BusFault_Handler");
 }
 
-/**
-  * @brief This function handles Undefined instruction or illegal state.
-  */
 void UsageFault_Handler(void)
 {
-  /* USER CODE BEGIN UsageFault_IRQn 0 */
-
-  /* USER CODE END UsageFault_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
-    /* USER CODE END W1_UsageFault_IRQn 0 */
-  }
+  Debug_TrapWithRttHint("UsageFault_Handler");
 }
 
-/**
-  * @brief This function handles Debug monitor.
-  */
 void DebugMon_Handler(void)
 {
-  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
-
-  /* USER CODE END DebugMonitor_IRQn 0 */
-  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
-  /* USER CODE END DebugMonitor_IRQn 1 */
 }
 
-/**
-  * @brief This function handles System tick timer.
-  */
 void SysTick_Handler(void)
 {
-  /* USER CODE BEGIN SysTick_IRQn 0 */
-
-  /* USER CODE END SysTick_IRQn 0 */
   HAL_IncTick();
-#if (INCLUDE_xTaskGetSchedulerState == 1 )
-  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
-  {
-#endif /* INCLUDE_xTaskGetSchedulerState */
-  xPortSysTickHandler();
-#if (INCLUDE_xTaskGetSchedulerState == 1 )
-  }
-#endif /* INCLUDE_xTaskGetSchedulerState */
-  /* USER CODE BEGIN SysTick_IRQn 1 */
-
-  /* USER CODE END SysTick_IRQn 1 */
 }
 
-/******************************************************************************/
-/* STM32F1xx Peripheral Interrupt Handlers                                    */
-/* Add here the Interrupt Handlers for the used peripherals.                  */
-/* For the available peripheral interrupt handler names,                      */
-/* please refer to the startup file (startup_stm32f1xx.s).                    */
-/******************************************************************************/
-
-/**
-  * @brief This function handles DMA1 channel2 global interrupt.
-  */
 void DMA1_Channel2_IRQHandler(void)
 {
-  /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
-
-  /* USER CODE END DMA1_Channel2_IRQn 0 */
   HAL_DMA_IRQHandler(&hdma_usart3_tx);
-  /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
-
-  /* USER CODE END DMA1_Channel2_IRQn 1 */
 }
 
-/**
-  * @brief This function handles DMA1 channel3 global interrupt.
-  */
 void DMA1_Channel3_IRQHandler(void)
 {
-  /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */
-
-  /* USER CODE END DMA1_Channel3_IRQn 0 */
   HAL_DMA_IRQHandler(&hdma_usart3_rx);
-  /* USER CODE BEGIN DMA1_Channel3_IRQn 1 */
-
-  /* USER CODE END DMA1_Channel3_IRQn 1 */
 }
 
-/**
-  * @brief This function handles DMA1 channel4 global interrupt.
-  */
 void DMA1_Channel4_IRQHandler(void)
 {
-  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
-
-  /* USER CODE END DMA1_Channel4_IRQn 0 */
   HAL_DMA_IRQHandler(&hdma_usart1_tx);
-  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
-
-  /* USER CODE END DMA1_Channel4_IRQn 1 */
 }
 
-/**
-  * @brief This function handles DMA1 channel5 global interrupt.
-  */
 void DMA1_Channel5_IRQHandler(void)
 {
-  /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */
-
-  /* USER CODE END DMA1_Channel5_IRQn 0 */
   HAL_DMA_IRQHandler(&hdma_usart1_rx);
-  /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */
-
-  /* USER CODE END DMA1_Channel5_IRQn 1 */
 }
 
-/**
-  * @brief This function handles DMA1 channel6 global interrupt.
-  */
 void DMA1_Channel6_IRQHandler(void)
 {
-  /* USER CODE BEGIN DMA1_Channel6_IRQn 0 */
-
-  /* USER CODE END DMA1_Channel6_IRQn 0 */
   HAL_DMA_IRQHandler(&hdma_usart2_rx);
-  /* USER CODE BEGIN DMA1_Channel6_IRQn 1 */
-
-  /* USER CODE END DMA1_Channel6_IRQn 1 */
 }
 
-/**
-  * @brief This function handles DMA1 channel7 global interrupt.
-  */
 void DMA1_Channel7_IRQHandler(void)
 {
-  /* USER CODE BEGIN DMA1_Channel7_IRQn 0 */
-
-  /* USER CODE END DMA1_Channel7_IRQn 0 */
   HAL_DMA_IRQHandler(&hdma_usart2_tx);
-  /* USER CODE BEGIN DMA1_Channel7_IRQn 1 */
-
-  /* USER CODE END DMA1_Channel7_IRQn 1 */
 }
 
-/**
-  * @brief This function handles SPI1 global interrupt.
-  */
+void TIM4_IRQHandler(void)
+{
+  HAL_TIM_IRQHandler(&htim4);
+}
+
 void SPI1_IRQHandler(void)
 {
-  /* USER CODE BEGIN SPI1_IRQn 0 */
-
-  /* USER CODE END SPI1_IRQn 0 */
   HAL_SPI_IRQHandler(&hspi1);
-  /* USER CODE BEGIN SPI1_IRQn 1 */
-
-  /* USER CODE END SPI1_IRQn 1 */
 }
 
-/**
-  * @brief This function handles USART1 global interrupt.
-  */
 void USART1_IRQHandler(void)
 {
-  /* USER CODE BEGIN USART1_IRQn 0 */
-  /* Handle IDLE interrupt for configuration */
-  if (__HAL_UART_GET_FLAG(&huart1, UART_FLAG_IDLE))
-  {
-    __HAL_UART_CLEAR_IDLEFLAG(&huart1);
-    config_uart_idle_handler();
-  }
-  /* USER CODE END USART1_IRQn 0 */
   HAL_UART_IRQHandler(&huart1);
-  /* USER CODE BEGIN USART1_IRQn 1 */
-
-  /* USER CODE END USART1_IRQn 1 */
 }
 
-/**
-  * @brief This function handles USART2 global interrupt.
-  */
 void USART2_IRQHandler(void)
 {
-  /* USER CODE BEGIN USART2_IRQn 0 */
-  /* Handle IDLE interrupt for Server transparent transmission */
   if (__HAL_UART_GET_FLAG(&huart2, UART_FLAG_IDLE))
   {
     __HAL_UART_CLEAR_IDLEFLAG(&huart2);
-    uart_trans_idle_handler(UART_CHANNEL_SERVER);
+    uart_trans_idle_handler(UART_CHANNEL_U0);
   }
-  /* USER CODE END USART2_IRQn 0 */
   HAL_UART_IRQHandler(&huart2);
-  /* USER CODE BEGIN USART2_IRQn 1 */
-
-  /* USER CODE END USART2_IRQn 1 */
 }
 
-/**
-  * @brief This function handles USART3 global interrupt.
-  */
 void USART3_IRQHandler(void)
 {
-  /* USER CODE BEGIN USART3_IRQn 0 */
-  /* Handle IDLE interrupt for Client transparent transmission */
   if (__HAL_UART_GET_FLAG(&huart3, UART_FLAG_IDLE))
   {
     __HAL_UART_CLEAR_IDLEFLAG(&huart3);
-    uart_trans_idle_handler(UART_CHANNEL_CLIENT);
+    uart_trans_idle_handler(UART_CHANNEL_U1);
   }
-  /* USER CODE END USART3_IRQn 0 */
   HAL_UART_IRQHandler(&huart3);
-  /* USER CODE BEGIN USART3_IRQn 1 */
-
-  /* USER CODE END USART3_IRQn 1 */
 }
 
-/* USER CODE BEGIN 1 */
-/**
-  * @brief This function handles EXTI0 interrupt (CH390D INT pin).
-  */
 void EXTI0_IRQHandler(void)
 {
-  /* Clear interrupt flag */
   if (__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_0))
   {
     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_0);
-    
-    /* Notify LwIP task */
-    notify_ch390_interrupt_from_isr();
+    ethernetif_set_irq_pending();
   }
 }
 
-/**
-  * @brief HAL UART TX Complete callback
-  */
 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
 {
   if (huart == &huart2)
   {
-    uart_trans_tx_cplt_handler(UART_CHANNEL_SERVER);
+    uart_trans_tx_cplt_handler(UART_CHANNEL_U0);
   }
   else if (huart == &huart3)
   {
-    uart_trans_tx_cplt_handler(UART_CHANNEL_CLIENT);
+    uart_trans_tx_cplt_handler(UART_CHANNEL_U1);
   }
 }
 
-/**
-  * @brief HAL UART RX Complete callback
-  */
 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
 {
-  if (huart == &huart2)
+  if (huart == &huart1)
   {
-    uart_trans_rx_cplt_handler(UART_CHANNEL_SERVER);
+    config_uart_rx_byte(g_uart1_rx_probe_byte);
+    (void)HAL_UART_Receive_IT(&huart1, (uint8_t *)&g_uart1_rx_probe_byte, 1u);
+  }
+  else if (huart == &huart2)
+  {
+    uart_trans_rx_cplt_handler(UART_CHANNEL_U0);
   }
   else if (huart == &huart3)
   {
-    uart_trans_rx_cplt_handler(UART_CHANNEL_CLIENT);
+    uart_trans_rx_cplt_handler(UART_CHANNEL_U1);
   }
 }
 
-/**
-  * @brief HAL UART RX Half Complete callback
-  */
 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
 {
   if (huart == &huart2)
   {
-    uart_trans_rx_half_cplt_handler(UART_CHANNEL_SERVER);
+    uart_trans_rx_half_cplt_handler(UART_CHANNEL_U0);
   }
   else if (huart == &huart3)
   {
-    uart_trans_rx_half_cplt_handler(UART_CHANNEL_CLIENT);
+    uart_trans_rx_half_cplt_handler(UART_CHANNEL_U1);
   }
 }
-/* USER CODE END 1 */

Core/Src/syscalls.c

@@ -0,0 +1,245 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeMX
+ * @brief     Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib or Picolibc libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2020-2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include "main.h"
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdio.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+
+/* Variables */
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+  return 1;
+}
+
+int _kill(int pid, int sig)
+{
+  (void)pid;
+  (void)sig;
+  errno = EINVAL;
+  return -1;
+}
+
+void _exit (int status)
+{
+  _kill(status, -1);
+  Debug_TrapWithRttHint("_exit");
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+  (void)file;
+  int DataIdx;
+
+  for (DataIdx = 0; DataIdx < len; DataIdx++)
+  {
+    *ptr++ = __io_getchar();
+  }
+
+  return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+  (void)file;
+  int DataIdx;
+
+  for (DataIdx = 0; DataIdx < len; DataIdx++)
+  {
+    __io_putchar(*ptr++);
+  }
+  return len;
+}
+
+int _close(int file)
+{
+  (void)file;
+  return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+  (void)file;
+  st->st_mode = S_IFCHR;
+  return 0;
+}
+
+int _isatty(int file)
+{
+  (void)file;
+  return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+  (void)file;
+  (void)ptr;
+  (void)dir;
+  return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+  (void)path;
+  (void)flags;
+  /* Pretend like we always fail */
+  return -1;
+}
+
+int _wait(int *status)
+{
+  (void)status;
+  errno = ECHILD;
+  return -1;
+}
+
+int _unlink(char *name)
+{
+  (void)name;
+  errno = ENOENT;
+  return -1;
+}
+
+clock_t _times(struct tms *buf)
+{
+  (void)buf;
+  return -1;
+}
+
+int _stat(const char *file, struct stat *st)
+{
+  (void)file;
+  st->st_mode = S_IFCHR;
+  return 0;
+}
+
+int _link(char *old, char *new)
+{
+  (void)old;
+  (void)new;
+  errno = EMLINK;
+  return -1;
+}
+
+int _fork(void)
+{
+  errno = EAGAIN;
+  return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+  (void)name;
+  (void)argv;
+  (void)env;
+  errno = ENOMEM;
+  return -1;
+}
+
+// --- Picolibc Specific Section ---
+#if defined(__PICOLIBC__)
+
+/**
+ * @brief Picolibc helper function to output a character to a FILE stream.
+ *        This redirects the output to the low-level __io_putchar function.
+ * @param c Character to write.
+ * @param file FILE stream pointer (ignored).
+ * @retval int The character written.
+ */
+static int starm_putc(char c, FILE *file)
+{
+	(void) file;
+  __io_putchar(c);
+	return c;
+}
+
+/**
+ * @brief Picolibc helper function to input a character from a FILE stream.
+ *        This redirects the input from the low-level __io_getchar function.
+ * @param file FILE stream pointer (ignored).
+ * @retval int The character read, cast to an unsigned char then int.
+ */
+static int starm_getc(FILE *file)
+{
+	unsigned char c;
+	(void) file;
+  c = __io_getchar();
+	return c;
+}
+
+// Define and initialize the standard I/O streams for Picolibc.
+// FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure.
+// _FDEV_SETUP_RW indicates the stream is for reading and writing.
+static FILE __stdio = FDEV_SETUP_STREAM(starm_putc,
+					starm_getc,
+					NULL,
+					_FDEV_SETUP_RW);
+
+// Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream.
+// Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.).
+FILE *const stdin = &__stdio;
+__strong_reference(stdin, stdout);
+__strong_reference(stdin, stderr);
+
+// Create strong aliases mapping standard C library function names (without underscore)
+// to the implemented system call stubs (with underscore). Picolibc uses these
+// standard names internally, so this linking is required.
+__strong_reference(_read, read);
+__strong_reference(_write, write);
+__strong_reference(_times, times);
+__strong_reference(_execve, execve);
+__strong_reference(_fork, fork);
+__strong_reference(_link, link);
+__strong_reference(_unlink, unlink);
+__strong_reference(_stat, stat);
+__strong_reference(_wait, wait);
+__strong_reference(_open, open);
+__strong_reference(_close, close);
+__strong_reference(_lseek, lseek);
+__strong_reference(_isatty, isatty);
+__strong_reference(_fstat, fstat);
+__strong_reference(_exit, exit);
+__strong_reference(_kill, kill);
+__strong_reference(_getpid, getpid);
+
+#endif //__PICOLIBC__

Core/Src/sysmem.c

@@ -0,0 +1,87 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Generated by STM32CubeMX
+ * @brief     System Memory calls file
+ *
+ *            For more information about which C functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib or Picolibc libc manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include <errno.h>
+#include <stdint.h>
+#include <stddef.h>
+
+/**
+ * Pointer to the current high watermark of the heap usage
+ */
+static uint8_t *__sbrk_heap_end = NULL;
+
+/**
+ * @brief _sbrk() allocates memory to the newlib heap and is used by malloc
+ *        and others from the C library
+ *
+ * @verbatim
+ * ############################################################################
+ * #  .data  #  .bss  #       newlib heap       #          MSP stack          #
+ * #         #        #                         # Reserved by _Min_Stack_Size #
+ * ############################################################################
+ * ^-- RAM start      ^-- _end                             _estack, RAM end --^
+ * @endverbatim
+ *
+ * This implementation starts allocating at the '_end' linker symbol
+ * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
+ * The implementation considers '_estack' linker symbol to be RAM end
+ * NOTE: If the MSP stack, at any point during execution, grows larger than the
+ * reserved size, please increase the '_Min_Stack_Size'.
+ *
+ * @param incr Memory size
+ * @return Pointer to allocated memory
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+  extern uint8_t _end; /* Symbol defined in the linker script */
+  extern uint8_t _estack; /* Symbol defined in the linker script */
+  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+  const uint8_t *max_heap = (uint8_t *)stack_limit;
+  uint8_t *prev_heap_end;
+
+  /* Initialize heap end at first call */
+  if (NULL == __sbrk_heap_end)
+  {
+    __sbrk_heap_end = &_end;
+  }
+
+  /* Protect heap from growing into the reserved MSP stack */
+  if (__sbrk_heap_end + incr > max_heap)
+  {
+    errno = ENOMEM;
+    return (void *)-1;
+  }
+
+  prev_heap_end = __sbrk_heap_end;
+  __sbrk_heap_end += incr;
+
+  return (void *)prev_heap_end;
+}
+
+#if defined(__PICOLIBC__)
+  // Picolibc expects syscalls without the leading underscore.
+  // This creates a strong alias so that
+  // calls to `sbrk()` are resolved to our `_sbrk()` implementation.
+  __strong_reference(_sbrk, sbrk);
+#endif

Core/Src/tim.c

@@ -0,0 +1,100 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.c
+  * @brief   This file provides code for the configuration of the TIM instances.
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "tim.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+TIM_HandleTypeDef htim4;
+
+/* TIM4 init function */
+void MX_TIM4_Init(void)
+{
+
+  /* USER CODE BEGIN TIM4_Init 0 */
+
+  /* USER CODE END TIM4_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM4_Init 1 */
+
+  /* USER CODE END TIM4_Init 1 */
+  htim4.Instance = TIM4;
+  htim4.Init.Prescaler = 7199;
+  htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim4.Init.Period = 9;
+  htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM4_Init 2 */
+
+  /* USER CODE END TIM4_Init 2 */
+
+}
+
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  if(tim_baseHandle->Instance==TIM4)
+  {
+  /* USER CODE BEGIN TIM4_MspInit 0 */
+
+  /* USER CODE END TIM4_MspInit 0 */
+    /* TIM4 clock enable */
+    __HAL_RCC_TIM4_CLK_ENABLE();
+
+    /* TIM4 interrupt Init */
+    HAL_NVIC_SetPriority(TIM4_IRQn, 6, 0);
+    HAL_NVIC_EnableIRQ(TIM4_IRQn);
+  /* USER CODE BEGIN TIM4_MspInit 1 */
+
+  /* USER CODE END TIM4_MspInit 1 */
+  }
+}
+
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  if(tim_baseHandle->Instance==TIM4)
+  {
+  /* USER CODE BEGIN TIM4_MspDeInit 0 */
+
+  /* USER CODE END TIM4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM4_CLK_DISABLE();
+
+    /* TIM4 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(TIM4_IRQn);
+  /* USER CODE BEGIN TIM4_MspDeInit 1 */
+
+  /* USER CODE END TIM4_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */

Drivers/CH390/CH390.c

@@ -12,6 +12,8 @@
 #include "CH390.h"
 #include "CH390_Interface.h"
 
+#define CH390_PHY_BUSY_TIMEOUT_LOOPS 2000u
+
 /**
  * @name ch390_receive_packet
  * @brief Receive packet
@@ -119,10 +121,17 @@ void ch390_drop_packet(uint16_t len)
  */
 uint16_t ch390_read_phy(uint8_t reg)
 {
+    uint32_t timeout = CH390_PHY_BUSY_TIMEOUT_LOOPS;
+
     ch390_write_reg(CH390_EPAR, CH390_PHY | reg);
     // Chose PHY, send read command
     ch390_write_reg(CH390_EPCR, EPCR_ERPRR | EPCR_EPOS);
-    while(ch390_read_reg(CH390_EPCR) & 0x01);
+    while ((ch390_read_reg(CH390_EPCR) & EPCR_ERRE) != 0u) {
+        if (timeout-- == 0u) {
+            ch390_write_reg(CH390_EPCR, 0x00);
+            return 0;
+        }
+    }
     // Clear read command
     ch390_write_reg(CH390_EPCR, 0x00);
     return (ch390_read_reg(CH390_EPDRH) << 8) |
@@ -137,12 +146,19 @@ uint16_t ch390_read_phy(uint8_t reg)
  */
 void ch390_write_phy(uint8_t reg, uint16_t value)
 {
+    uint32_t timeout = CH390_PHY_BUSY_TIMEOUT_LOOPS;
+
     ch390_write_reg(CH390_EPAR, CH390_PHY | reg);
     ch390_write_reg(CH390_EPDRL, (value & 0xff));        // Low byte
     ch390_write_reg(CH390_EPDRH, ((value >> 8) & 0xff)); // High byte
     // Chose PHY, send write command
     ch390_write_reg(CH390_EPCR, 0x0A);
-    while(ch390_read_reg(CH390_EPCR) & 0x01);
+    while ((ch390_read_reg(CH390_EPCR) & EPCR_ERRE) != 0u) {
+        if (timeout-- == 0u) {
+            ch390_write_reg(CH390_EPCR, 0x00);
+            return;
+        }
+    }
     // Clear write command
     ch390_write_reg(CH390_EPCR, 0x00);
 }
@@ -194,6 +210,7 @@ void ch390_default_config()
     uint8_t multicase_addr[8] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
 
     ch390_set_phy_mode(CH390_AUTO);
+    ch390_write_reg(CH390_INTCR, (uint8_t)(INCR_TYPE_OD | INCR_POL_L));
     // Clear status
     ch390_write_reg(CH390_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
     ch390_write_reg(CH390_ISR, 0xFF);         // Clear interrupt status
@@ -203,9 +220,9 @@ void ch390_default_config()
     // ch390_set_mac_address(mac_addr);
     ch390_set_multicast(multicase_addr);
 
-    // Enable all interrupt and PAR
-    ch390_write_reg(CH390_IMR, IMR_ALL);
-    // Enable RX
+    // Enable only the interrupts needed by the NO_SYS polling path.
+    ch390_write_reg(CH390_IMR, (uint8_t)(IMR_PRI | IMR_LNKCHGI | IMR_ROOI | IMR_ROI));
+    // Enable RX with the reference receive filter.
     ch390_write_reg(CH390_RCR, RCR_DIS_CRC | RCR_RXEN);
 }
 

Drivers/CH390/CH390_Interface.c

@@ -12,8 +12,10 @@
  * Modified for STM32F103 HAL Library with FreeRTOS support.
  ******************************************************************************/
 #include "stm32f1xx_hal.h"
+#include "main.h"
 #include "CH390.h"
 #include "CH390_Interface.h"
+#include "SEGGER_RTT.h"
 
 /* FreeRTOS includes */
 #ifdef USE_FREERTOS
@@ -46,11 +48,19 @@
 #define CH390_INT_PORT      GPIOB
 #define CH390_INT_PIN       GPIO_PIN_0
 
+#define CH390_SCK_PORT      GPIOA
+#define CH390_SCK_PIN       GPIO_PIN_5
+#define CH390_MISO_PORT     GPIOA
+#define CH390_MISO_PIN      GPIO_PIN_6
+#define CH390_MOSI_PORT     GPIOA
+#define CH390_MOSI_PIN      GPIO_PIN_7
+
 /* External SPI handle from spi.c */
 extern SPI_HandleTypeDef hspi1;
 
 /* Timeout for SPI operations (ms) */
 #define SPI_TIMEOUT         100
+#define CH390_SPI_CHUNK_SIZE 64u
 
 /*----------------------------------------------------------------------------
  * Low-level GPIO operations
@@ -64,6 +74,7 @@ static inline void ch390_cs(uint8_t state)
 {
     HAL_GPIO_WritePin(CH390_CS_PORT, CH390_CS_PIN, 
                       state ? GPIO_PIN_SET : GPIO_PIN_RESET);
+    ch390_delay_us(2);
 }
 
 /**
@@ -88,10 +99,42 @@ static inline void ch390_rst(uint8_t state)
 static uint8_t ch390_spi_exchange_byte(uint8_t byte)
 {
     uint8_t rx_data = 0;
-    HAL_SPI_TransmitReceive(&hspi1, &byte, &rx_data, 1, SPI_TIMEOUT);
+    if (HAL_SPI_TransmitReceive(&hspi1, &byte, &rx_data, 1, SPI_TIMEOUT) != HAL_OK)
+    {
+        return 0;
+    }
     return rx_data;
 }
 
+static int ch390_spi_read_bytes(uint8_t *data, uint16_t length)
+{
+    static const uint8_t dummy_tx[CH390_SPI_CHUNK_SIZE] = {0};
+
+    while (length > 0u)
+    {
+        uint16_t chunk = (length > CH390_SPI_CHUNK_SIZE) ? CH390_SPI_CHUNK_SIZE : length;
+        if (HAL_SPI_TransmitReceive(&hspi1, (uint8_t *)dummy_tx, data, chunk, SPI_TIMEOUT) != HAL_OK)
+        {
+            return -1;
+        }
+        data += chunk;
+        length = (uint16_t)(length - chunk);
+    }
+
+    return 0;
+}
+
+static void ch390_spi_apply_mode(uint32_t polarity, uint32_t phase)
+{
+    hspi1.Init.CLKPolarity = polarity;
+    hspi1.Init.CLKPhase = phase;
+    hspi1.Init.NSS = SPI_NSS_SOFT;
+    if (HAL_SPI_Init(&hspi1) != HAL_OK)
+    {
+        Error_Handler();
+    }
+}
+
 /**
  * @brief Read a dummy byte (send 0x00)
  * @return Received byte
@@ -156,20 +199,9 @@ void ch390_interrupt_init(void)
 void ch390_spi_init(void)
 {
     /* SPI1 is initialized by MX_SPI1_Init() in main.c */
-    /* We need to ensure correct SPI mode for CH390: */
-    /* - CPOL = High (idle clock is high) */
-    /* - CPHA = 2Edge (data captured on second edge) */
-    
-    /* Reconfigure SPI for CH390 if needed */
-    hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
-    hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
-    hspi1.Init.NSS = SPI_NSS_SOFT;  /* We control CS manually */
-    
-    if (HAL_SPI_Init(&hspi1) != HAL_OK)
-    {
-        /* Handle error */
-        Error_Handler();
-    }
+    /* Reference CH390 SPI path uses mode 3. */
+    ch390_spi_apply_mode(SPI_POLARITY_HIGH, SPI_PHASE_2EDGE);
+    SEGGER_RTT_WriteString(0, "CH390 SPI mode=3 (CPOL=1 CPHA=1)\r\n");
 }
 
 /**
@@ -220,10 +252,11 @@ void ch390_delay_us(uint32_t time)
  */
 void ch390_hardware_reset(void)
 {
+    ch390_delay_us(10000);      /* Short delay before reset */
     ch390_rst(0);               /* Assert reset (low) */
-    ch390_delay_us(100);        /* Hold reset for 100us (min 10us required) */
+    ch390_delay_us(3000);       /* Hold reset for 3ms to satisfy datasheet minimum */
     ch390_rst(1);               /* Release reset (high) */
-    ch390_delay_us(10000);      /* Wait 10ms for CH390 to initialize */
+    ch390_delay_us(50000);      /* Wait 50ms for CH390 to initialize reliably */
 }
 
 /*----------------------------------------------------------------------------
@@ -255,8 +288,8 @@ uint8_t ch390_read_reg(uint8_t reg)
 void ch390_write_reg(uint8_t reg, uint8_t value)
 {
     ch390_cs(0);                                /* CS low - select */
-    ch390_spi_exchange_byte(reg | OPC_REG_W);   /* Send write command */
-    ch390_spi_exchange_byte(value);             /* Write register value */
+    (void)ch390_spi_exchange_byte(reg | OPC_REG_W);
+    (void)ch390_spi_exchange_byte(value);
     ch390_cs(1);                                /* CS high - deselect */
 }
 
@@ -267,16 +300,15 @@ void ch390_write_reg(uint8_t reg, uint8_t value)
  */
 void ch390_read_mem(uint8_t *data, int length)
 {
-    int i;
+    if (data == NULL || length <= 0)
+    {
+        return;
+    }
 
     ch390_cs(0);                                /* CS low - select */
     ch390_spi_exchange_byte(OPC_MEM_READ);      /* Send memory read command */
 
-    /* Read data bytes */
-    for (i = 0; i < length; i++)
-    {
-        data[i] = ch390_spi_dummy_read();
-    }
+    (void)ch390_spi_read_bytes(data, (uint16_t)length);
     
     ch390_cs(1);                                /* CS high - deselect */
 }
@@ -308,16 +340,15 @@ void ch390_read_mem_dma(uint8_t *data, int length)
  */
 void ch390_write_mem(uint8_t *data, int length)
 {
-    int i;
+    if (data == NULL || length <= 0)
+    {
+        return;
+    }
 
     ch390_cs(0);                                /* CS low - select */
     ch390_spi_exchange_byte(OPC_MEM_WRITE);     /* Send memory write command */
 
-    /* Write data bytes */
-    for (i = 0; i < length; i++)
-    {
-        ch390_spi_exchange_byte(data[i]);
-    }
+    (void)HAL_SPI_Transmit(&hspi1, data, (uint16_t)length, SPI_TIMEOUT);
     
     ch390_cs(1);                                /* CS high - deselect */
 }

Drivers/CH390/ch390_runtime.c

@@ -0,0 +1,445 @@
+#include "ch390_runtime.h"
+
+#include "CH390.h"
+#include "CH390_Interface.h"
+#include "SEGGER_RTT.h"
+#include "ethernetif.h"
+#include "stm32f1xx_hal.h"
+#include "lwip/etharp.h"
+#include "lwip/pbuf.h"
+#include "lwip/stats.h"
+
+#include <string.h>
+
+static void ch390_runtime_dispatch_frame(struct netif *netif, struct pbuf *p)
+{
+    if ((p != NULL) && (netif->input(p, netif) != ERR_OK)) {
+        pbuf_free(p);
+    }
+}
+
+static uint8_t ch390_runtime_drain_rx(struct netif *netif, uint8_t max_frames)
+{
+    struct pbuf *p;
+    uint8_t drained = 0u;
+
+    while (drained < max_frames) {
+        p = ch390_runtime_input_frame(netif);
+        if (p == NULL) {
+            break;
+        }
+        ch390_runtime_dispatch_frame(netif, p);
+        drained++;
+    }
+
+    return drained;
+}
+
+static volatile uint8_t g_ch390_irq_pending;
+static uint8_t g_ch390_ready;
+static ch390_diag_t g_diag;
+static uint8_t g_tx_consecutive_timeout;
+static uint8_t g_chip_reset_count;
+
+#define TX_TIMEOUT_THRESHOLD  3u
+#define CHIP_RESET_MAX        3u
+
+#define TX_TIMEOUT_THRESHOLD  3u
+#define CHIP_RESET_MAX        3u
+
+static uint8_t ch390_runtime_probe_identity(void)
+{
+    g_diag.vendor_id = ch390_get_vendor_id();
+    g_diag.product_id = ch390_get_product_id();
+    g_diag.revision = ch390_get_revision();
+    g_diag.phy_bmcr = ch390_read_phy(CH390_PHY_BMCR);
+    g_diag.phy_bmsr = ch390_read_phy(CH390_PHY_BMSR);
+    g_diag.phy_id1 = ch390_read_phy(CH390_PHY_PHYID1);
+    g_diag.phy_id2 = ch390_read_phy(CH390_PHY_PHYID2);
+    g_diag.phy_anar = ch390_read_phy(CH390_PHY_ANAR);
+    g_diag.phy_anlpar = ch390_read_phy(CH390_PHY_ANLPAR);
+    g_diag.phy_aner = ch390_read_phy(CH390_PHY_ANER);
+    g_diag.nsr = ch390_read_reg(CH390_NSR);
+    g_diag.ncr = ch390_read_reg(CH390_NCR);
+    g_diag.rcr = ch390_read_reg(CH390_RCR);
+    g_diag.imr = ch390_read_reg(CH390_IMR);
+    g_diag.intcr = ch390_read_reg(CH390_INTCR);
+    g_diag.gpr = ch390_read_reg(CH390_GPR);
+    g_diag.isr = ch390_read_reg(CH390_ISR);
+    g_diag.phy_speed_10m = 0u;
+    g_diag.phy_full_duplex = 0u;
+    g_diag.link_up = (uint8_t)0u;
+    g_diag.id_valid = (uint8_t)((g_diag.vendor_id != 0x0000u) &&
+                                (g_diag.vendor_id != 0xFFFFu) &&
+                                (g_diag.product_id != 0x0000u) &&
+                                (g_diag.product_id != 0xFFFFu));
+    return g_diag.id_valid;
+}
+
+static void ch390_runtime_refresh_diag(void)
+{
+    uint8_t id_valid = ch390_runtime_probe_identity();
+    g_diag.int_pin = (uint8_t)ch390_get_int_pin();
+
+    if (id_valid != 0u) {
+        g_diag.phy_speed_10m = (uint8_t)ch390_get_phy_speed();
+        g_diag.phy_full_duplex = (uint8_t)ch390_get_duplex_mode();
+        g_diag.link_up = (uint8_t)ch390_get_link_status();
+    }
+}
+
+struct pbuf *ch390_runtime_input_frame(struct netif *netif)
+{
+    struct ethernetif *ethernetif = (struct ethernetif *)netif->state;
+    struct pbuf *p = NULL;
+    struct pbuf *q;
+    uint16_t len;
+    uint16_t frame_len;
+    uint8_t rcr;
+    uint8_t rx_ready;
+    uint8_t rx_header[4];
+    ch390_read_reg(CH390_MRCMDX);
+    rx_ready = ch390_read_reg(CH390_MRCMDX);
+
+    if (rx_ready & CH390_PKT_ERR) {
+        rcr = ch390_read_reg(CH390_RCR);
+        ch390_write_reg(CH390_RCR, (uint8_t)(rcr & (uint8_t)(~RCR_RXEN)));
+        ch390_write_reg(CH390_MPTRCR, 0x01u);
+        ch390_write_reg(CH390_MRRH, 0x0Cu);
+        ch390_delay_us(1000u);
+        ch390_write_reg(CH390_RCR, (uint8_t)(rcr | RCR_RXEN));
+        ethernetif->rx_len = 0u;
+        LINK_STATS_INC(link.drop);
+        g_diag.rx_packets_drop++;
+        return NULL;
+    }
+
+    if ((rx_ready & CH390_PKT_RDY) == 0u) {
+        ethernetif->rx_len = 0u;
+        return NULL;
+    }
+
+    g_diag.rx_ready_hits++;
+
+    ch390_read_mem(rx_header, 4);
+    ethernetif->rx_status = rx_header[1];
+    frame_len = (uint16_t)((uint16_t)rx_header[2] | ((uint16_t)rx_header[3] << 8));
+
+    if ((ethernetif->rx_status & 0x3Fu) != 0u || frame_len == 0u || frame_len > CH390_PKT_MAX) {
+        ethernetif->rx_len = 0u;
+        ch390_drop_packet(frame_len);
+        LINK_STATS_INC(link.drop);
+        g_diag.rx_packets_drop++;
+        return NULL;
+    }
+
+    ethernetif->rx_len = frame_len;
+    len = ethernetif->rx_len;
+#if ETH_PAD_SIZE
+    len += ETH_PAD_SIZE;
+#endif
+
+    p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+    if (p != NULL) {
+#if ETH_PAD_SIZE
+        pbuf_remove_header(p, ETH_PAD_SIZE);
+#endif
+        for (q = p; q != NULL; q = q->next) {
+            ch390_read_mem((uint8_t *)q->payload, q->len);
+        }
+#if ETH_PAD_SIZE
+        pbuf_add_header(p, ETH_PAD_SIZE);
+#endif
+        LINK_STATS_INC(link.recv);
+        g_diag.rx_packets_ok++;
+
+        g_diag.last_frame_len = frame_len;
+        g_diag.last_payload_len = p->tot_len;
+    } else {
+        ch390_drop_packet(ethernetif->rx_len);
+        LINK_STATS_INC(link.memerr);
+        LINK_STATS_INC(link.drop);
+        g_diag.rx_packets_drop++;
+    }
+
+    return p;
+}
+
+bool ch390_mac_address_valid(const uint8_t *mac)
+{
+    if (mac == NULL) {
+        return false;
+    }
+    for (uint8_t i = 0; i < ETHARP_HWADDR_LEN; ++i) {
+        if (mac[i] == 0u) {
+            return false;
+        }
+    }
+    return true;
+}
+
+void ch390_runtime_init(struct netif *netif, const uint8_t *mac)
+{
+    struct ethernetif *ethernetif = (struct ethernetif *)netif->state;
+
+    SEGGER_RTT_WriteString(0, "ETH init: gpio\r\n");
+    ch390_gpio_init();
+    SEGGER_RTT_WriteString(0, "ETH init: spi\r\n");
+    ch390_spi_init();
+    SEGGER_RTT_WriteString(0, "ETH init: reset\r\n");
+    ch390_hardware_reset();
+
+    SEGGER_RTT_WriteString(0, "ETH init: probe\r\n");
+    g_ch390_ready = ch390_runtime_probe_identity();
+    if (g_ch390_ready == 0u) {
+        netif->hwaddr_len = ETHARP_HWADDR_LEN;
+        netif->mtu = 1500;
+        netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET;
+
+        ethernetif->rx_len = 0u;
+        ethernetif->rx_status = 0u;
+
+        netif_set_link_down(netif);
+        SEGGER_RTT_WriteString(0, "ETH init: invalid chip id\r\n");
+        return;
+    }
+
+    SEGGER_RTT_WriteString(0, "ETH init: default\r\n");
+    ch390_default_config();
+    SEGGER_RTT_WriteString(0, "ETH init: mac\r\n");
+    if (ch390_mac_address_valid(mac)) {
+        ch390_set_mac_address((uint8_t *)mac);
+    }
+    else {
+        if (mac != NULL) {
+            ch390_get_mac((uint8_t *)mac);
+            SEGGER_RTT_printf(0, "ETH init: invalid MAC in config, using hardware MAC: %02X:%02X:%02X:%02X:%02X:%02X\r\n",
+                                  mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+        }
+        else {
+            SEGGER_RTT_WriteString(0, "ETH init: no MAC in config\r\n");
+        }
+    }
+
+    netif->hwaddr_len = ETHARP_HWADDR_LEN;
+    SEGGER_RTT_WriteString(0, "ETH init: getmac\r\n");
+    ch390_get_mac(netif->hwaddr);
+    netif->mtu = 1500;
+    netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET;
+
+    ethernetif->rx_len = 0u;
+    ethernetif->rx_status = 0u;
+
+    ch390_runtime_refresh_diag();
+    g_ch390_ready = g_diag.id_valid;
+
+    SEGGER_RTT_WriteString(0, "ETH init: irq\r\n");
+    ch390_interrupt_init();
+    SEGGER_RTT_WriteString(0, "ETH init: done\r\n");
+}
+
+void ch390_runtime_set_irq_pending(void)
+{
+    g_ch390_irq_pending = 1u;
+}
+
+uint8_t ch390_runtime_is_irq_pending(void)
+{
+    return g_ch390_irq_pending;
+}
+
+void ch390_runtime_poll(struct netif *netif)
+{
+    uint8_t int_status;
+    uint8_t rx_ready;
+    uint8_t rx_budget;
+    uint8_t rx_hint;
+
+    if (!g_ch390_ready) {
+        return;
+    }
+
+    g_diag.rx_poll_calls++;
+
+    rx_budget = 1u;
+    rx_hint = 0u;
+
+    if ((g_ch390_irq_pending != 0u) || (ch390_get_int_pin() == GPIO_PIN_RESET)) {
+        g_ch390_irq_pending = 0u;
+        int_status = ch390_get_int_status();
+
+        if ((int_status & ISR_LNKCHG) != 0u) {
+            ch390_runtime_check_link(netif);
+        }
+
+        if ((int_status & ISR_ROS) != 0u) {
+            LINK_STATS_INC(link.err);
+        }
+
+        if ((int_status & (ISR_PR | ISR_ROS | ISR_ROO)) != 0u) {
+            rx_hint = 1u;
+            rx_budget = 8u;
+        }
+    }
+
+    ch390_read_reg(CH390_MRCMDX);
+    rx_ready = ch390_read_reg(CH390_MRCMDX);
+    if ((rx_ready & CH390_PKT_RDY) != 0u) {
+        rx_hint = 1u;
+        if (rx_budget < 4u) {
+            rx_budget = 4u;
+        }
+    }
+
+    if (rx_hint != 0u) {
+        (void)ch390_runtime_drain_rx(netif, rx_budget);
+    }
+}
+
+void ch390_runtime_check_link(struct netif *netif)
+{
+    uint8_t link_up;
+    static uint8_t s_last_reported = 0xFFu;
+
+    if (!g_ch390_ready) {
+        netif_set_link_down(netif);
+        return;
+    }
+
+    ch390_runtime_refresh_diag();
+    link_up = (uint8_t)ch390_get_link_status();
+
+    if (link_up != s_last_reported) {
+        SEGGER_RTT_printf(0,
+                          "ETH link %s nsr=0x%02X bmsr=0x%04X anlpar=0x%04X\r\n",
+                          link_up ? "up" : "down",
+                          g_diag.nsr,
+                          g_diag.phy_bmsr,
+                          g_diag.phy_anlpar);
+        s_last_reported = link_up;
+    }
+
+    if (link_up) {
+        if (!netif_is_link_up(netif)) {
+            netif_set_link_up(netif);
+        }
+    } else if (netif_is_link_up(netif)) {
+        netif_set_link_down(netif);
+    }
+}
+
+err_t ch390_runtime_output(struct netif *netif, struct pbuf *p)
+{
+    struct pbuf *q;
+    uint32_t start_tick;
+
+    LWIP_UNUSED_ARG(netif);
+
+    if (!g_ch390_ready) {
+        LINK_STATS_INC(link.drop);
+        return ERR_IF;
+    }
+
+#if ETH_PAD_SIZE
+    pbuf_remove_header(p, ETH_PAD_SIZE);
+#endif
+
+    start_tick = HAL_GetTick();
+    while (ch390_read_reg(CH390_TCR) & TCR_TXREQ) {
+        if ((HAL_GetTick() - start_tick) > 10u) {
+#if ETH_PAD_SIZE
+            pbuf_add_header(p, ETH_PAD_SIZE);
+#endif
+            LINK_STATS_INC(link.drop);
+            g_diag.tx_packets_timeout++;
+            g_tx_consecutive_timeout++;
+            if (g_tx_consecutive_timeout >= TX_TIMEOUT_THRESHOLD) {
+                ch390_runtime_emergency_reset();
+            }
+            return ERR_TIMEOUT;
+        }
+    }
+
+    g_tx_consecutive_timeout = 0u;
+
+    for (q = p; q != NULL; q = q->next) {
+        ch390_write_mem((uint8_t *)q->payload, q->len);
+    }
+
+    ch390_write_reg(CH390_TXPLL, p->tot_len & 0xFFu);
+    ch390_write_reg(CH390_TXPLH, (p->tot_len >> 8) & 0xFFu);
+    ch390_send_request();
+
+#if ETH_PAD_SIZE
+    pbuf_add_header(p, ETH_PAD_SIZE);
+#endif
+
+    LINK_STATS_INC(link.xmit);
+    g_diag.tx_packets_ok++;
+    return ERR_OK;
+}
+
+void ch390_runtime_get_diag(ch390_diag_t *diag)
+{
+    if (diag != NULL) {
+        ch390_runtime_refresh_diag();
+        *diag = g_diag;
+    }
+}
+
+bool ch390_runtime_is_ready(void)
+{
+    return g_ch390_ready != 0u;
+}
+
+bool ch390_runtime_emergency_reset(void)
+{
+    SEGGER_RTT_printf(0, "ETH emergency reset (tx_timeout=%u resets=%u/%u)\r\n",
+                      g_tx_consecutive_timeout, g_chip_reset_count, CHIP_RESET_MAX);
+
+    if (g_chip_reset_count >= CHIP_RESET_MAX) {
+        SEGGER_RTT_WriteString(0, "ETH: max resets reached, giving up\r\n");
+        g_ch390_ready = 0u;
+        return false;
+    }
+
+    g_chip_reset_count++;
+    g_tx_consecutive_timeout = 0u;
+
+    ch390_software_reset();
+    ch390_delay_us(5000u);
+    ch390_default_config();
+
+    ch390_runtime_refresh_diag();
+    g_ch390_ready = g_diag.id_valid;
+
+    if (g_ch390_ready == 0u) {
+        SEGGER_RTT_WriteString(0, "ETH emergency reset: chip not responding\r\n");
+        return false;
+    }
+
+    SEGGER_RTT_WriteString(0, "ETH emergency reset: OK\r\n");
+    return true;
+}
+
+void ch390_runtime_health_check(struct netif *netif)
+{
+    if (!g_ch390_ready) {
+        return;
+    }
+
+    /* Verify chip is still responding by reading vendor ID */
+    uint16_t vid = ch390_get_vendor_id();
+    if (vid == 0x0000u || vid == 0xFFFFu) {
+        SEGGER_RTT_printf(0, "ETH health: invalid VID=0x%04X, attempting reset\r\n", vid);
+        netif_set_link_down(netif);
+        if (ch390_runtime_emergency_reset()) {
+            ch390_runtime_check_link(netif);
+        }
+    }
+}
+
+uint8_t ch390_runtime_get_reset_count(void)
+{
+    return g_chip_reset_count;
+}

Drivers/CH390/ch390_runtime.h

@@ -0,0 +1,65 @@
+#ifndef __CH390_RUNTIME_H__
+#define __CH390_RUNTIME_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "lwip/err.h"
+
+struct netif;
+struct pbuf;
+
+typedef struct {
+    uint16_t vendor_id;
+    uint16_t product_id;
+    uint8_t revision;
+    uint16_t phy_bmcr;
+    uint16_t phy_bmsr;
+    uint16_t phy_id1;
+    uint16_t phy_id2;
+    uint16_t phy_anar;
+    uint16_t phy_anlpar;
+    uint16_t phy_aner;
+    uint8_t nsr;
+    uint8_t ncr;
+    uint8_t rcr;
+    uint8_t imr;
+    uint8_t intcr;
+    uint8_t gpr;
+    uint8_t isr;
+    uint8_t int_pin;
+    uint8_t phy_speed_10m;
+    uint8_t phy_full_duplex;
+    uint8_t link_up;
+    uint8_t id_valid;
+    uint32_t rx_poll_calls;
+    uint32_t rx_ready_hits;
+    uint32_t rx_packets_ok;
+    uint32_t rx_packets_drop;
+    uint32_t tx_packets_ok;
+    uint32_t tx_packets_timeout;
+    uint32_t rx_arp_frames;
+    uint32_t rx_ip_frames;
+    uint32_t rx_other_frames;
+    uint32_t rx_unicast_self_frames;
+    uint32_t rx_broadcast_frames;
+    uint32_t rx_multicast_frames;
+    uint16_t last_frame_len;
+    uint16_t last_payload_len;
+    uint16_t last_eth_type;
+} ch390_diag_t;
+
+void ch390_runtime_init(struct netif *netif, const uint8_t *mac);
+struct pbuf *ch390_runtime_input_frame(struct netif *netif);
+void ch390_runtime_set_irq_pending(void);
+uint8_t ch390_runtime_is_irq_pending(void);
+void ch390_runtime_poll(struct netif *netif);
+void ch390_runtime_check_link(struct netif *netif);
+err_t ch390_runtime_output(struct netif *netif, struct pbuf *p);
+void ch390_runtime_get_diag(ch390_diag_t *diag);
+bool ch390_runtime_is_ready(void);
+bool ch390_runtime_emergency_reset(void);
+void ch390_runtime_health_check(struct netif *netif);
+uint8_t ch390_runtime_get_reset_count(void);
+
+#endif

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f100xb.s

@@ -1,313 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f100xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32F100xB Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                    ; Top of Stack
-                DCD     Reset_Handler                   ; Reset Handler
-                DCD     NMI_Handler                     ; NMI Handler
-                DCD     HardFault_Handler               ; Hard Fault Handler
-                DCD     MemManage_Handler               ; MPU Fault Handler
-                DCD     BusFault_Handler                ; Bus Fault Handler
-                DCD     UsageFault_Handler              ; Usage Fault Handler
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     SVC_Handler                     ; SVCall Handler
-                DCD     DebugMon_Handler                ; Debug Monitor Handler
-                DCD     0                               ; Reserved
-                DCD     PendSV_Handler                  ; PendSV Handler
-                DCD     SysTick_Handler                 ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                 ; Window Watchdog
-                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler               ; Tamper
-                DCD     RTC_IRQHandler                  ; RTC
-                DCD     FLASH_IRQHandler                ; Flash
-                DCD     RCC_IRQHandler                  ; RCC
-                DCD     EXTI0_IRQHandler                ; EXTI Line 0
-                DCD     EXTI1_IRQHandler                ; EXTI Line 1
-                DCD     EXTI2_IRQHandler                ; EXTI Line 2
-                DCD     EXTI3_IRQHandler                ; EXTI Line 3
-                DCD     EXTI4_IRQHandler                ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler                 ; ADC1
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
-                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
-                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
-                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
-                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler                 ; TIM2
-                DCD     TIM3_IRQHandler                 ; TIM3
-                DCD     TIM4_IRQHandler                 ; TIM4
-                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler              ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler              ; I2C2 Error
-                DCD     SPI1_IRQHandler                 ; SPI1
-                DCD     SPI2_IRQHandler                 ; SPI2
-                DCD     USART1_IRQHandler               ; USART1
-                DCD     USART2_IRQHandler               ; USART2
-                DCD     USART3_IRQHandler               ; USART3
-                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler             ; RTC Alarm through EXTI Line
-                DCD     CEC_IRQHandler                  ; HDMI-CEC
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved 
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved 
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
-                DCD     TIM7_IRQHandler                 ; TIM7
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                      [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler                [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler                [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler                 [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler               [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                      [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler                 [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                   [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                  [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                  [WEAK]
-                EXPORT  PVD_IRQHandler                   [WEAK]
-                EXPORT  TAMPER_IRQHandler                [WEAK]
-                EXPORT  RTC_IRQHandler                   [WEAK]
-                EXPORT  FLASH_IRQHandler                 [WEAK]
-                EXPORT  RCC_IRQHandler                   [WEAK]
-                EXPORT  EXTI0_IRQHandler                 [WEAK]
-                EXPORT  EXTI1_IRQHandler                 [WEAK]
-                EXPORT  EXTI2_IRQHandler                 [WEAK]
-                EXPORT  EXTI3_IRQHandler                 [WEAK]
-                EXPORT  EXTI4_IRQHandler                 [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
-                EXPORT  ADC1_IRQHandler                  [WEAK]
-                EXPORT  EXTI9_5_IRQHandler               [WEAK]
-                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler               [WEAK]
-                EXPORT  TIM2_IRQHandler                  [WEAK]
-                EXPORT  TIM3_IRQHandler                  [WEAK]
-                EXPORT  TIM4_IRQHandler                  [WEAK]
-                EXPORT  I2C1_EV_IRQHandler               [WEAK]
-                EXPORT  I2C1_ER_IRQHandler               [WEAK]
-                EXPORT  I2C2_EV_IRQHandler               [WEAK]
-                EXPORT  I2C2_ER_IRQHandler               [WEAK]
-                EXPORT  SPI1_IRQHandler                  [WEAK]
-                EXPORT  SPI2_IRQHandler                  [WEAK]
-                EXPORT  USART1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler                [WEAK]
-                EXPORT  USART3_IRQHandler                [WEAK]
-                EXPORT  EXTI15_10_IRQHandler             [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
-                EXPORT  CEC_IRQHandler                   [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
-                EXPORT  TIM7_IRQHandler                  [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM15_IRQHandler
-TIM1_UP_TIM16_IRQHandler
-TIM1_TRG_COM_TIM17_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-CEC_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f100xe.s

@@ -1,344 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f100xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32F100xE Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system and also configure the external 
-;*                        SRAM mounted on STM32100E-EVAL board to be used as data 
-;*                        memory (optional, to be enabled by user)
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                    ; Top of Stack
-                DCD     Reset_Handler                   ; Reset Handler
-                DCD     NMI_Handler                     ; NMI Handler
-                DCD     HardFault_Handler               ; Hard Fault Handler
-                DCD     MemManage_Handler               ; MPU Fault Handler
-                DCD     BusFault_Handler                ; Bus Fault Handler
-                DCD     UsageFault_Handler              ; Usage Fault Handler
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     SVC_Handler                     ; SVCall Handler
-                DCD     DebugMon_Handler                ; Debug Monitor Handler
-                DCD     0                               ; Reserved
-                DCD     PendSV_Handler                  ; PendSV Handler
-                DCD     SysTick_Handler                 ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                 ; Window Watchdog
-                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler               ; Tamper
-                DCD     RTC_IRQHandler                  ; RTC
-                DCD     FLASH_IRQHandler                ; Flash
-                DCD     RCC_IRQHandler                  ; RCC
-                DCD     EXTI0_IRQHandler                ; EXTI Line 0
-                DCD     EXTI1_IRQHandler                ; EXTI Line 1
-                DCD     EXTI2_IRQHandler                ; EXTI Line 2
-                DCD     EXTI3_IRQHandler                ; EXTI Line 3
-                DCD     EXTI4_IRQHandler                ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler                 ; ADC1
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
-                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
-                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
-                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
-                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler                 ; TIM2
-                DCD     TIM3_IRQHandler                 ; TIM3
-                DCD     TIM4_IRQHandler                 ; TIM4
-                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler              ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler              ; I2C2 Error
-                DCD     SPI1_IRQHandler                 ; SPI1
-                DCD     SPI2_IRQHandler                 ; SPI2
-                DCD     USART1_IRQHandler               ; USART1
-                DCD     USART2_IRQHandler               ; USART2
-                DCD     USART3_IRQHandler               ; USART3
-                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler             ; RTC Alarm through EXTI Line
-                DCD     CEC_IRQHandler                  ; HDMI CEC
-                DCD     TIM12_IRQHandler                ; TIM12
-                DCD     TIM13_IRQHandler                ; TIM13 
-                DCD     TIM14_IRQHandler                ; TIM14
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     TIM5_IRQHandler                 ; TIM5
-                DCD     SPI3_IRQHandler                 ; SPI3
-                DCD     UART4_IRQHandler                ; UART4
-                DCD     UART5_IRQHandler                ; UART5
-                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
-                DCD     TIM7_IRQHandler                 ; TIM7
-                DCD     DMA2_Channel1_IRQHandler        ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler        ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler        ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler      ; DMA2 Channel4 & Channel5
-                DCD     DMA2_Channel5_IRQHandler        ; DMA2 Channel5                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                      [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler                [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler                [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler                 [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler               [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                      [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler                 [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                   [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                  [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                  [WEAK]
-                EXPORT  PVD_IRQHandler                   [WEAK]
-                EXPORT  TAMPER_IRQHandler                [WEAK]
-                EXPORT  RTC_IRQHandler                   [WEAK]
-                EXPORT  FLASH_IRQHandler                 [WEAK]
-                EXPORT  RCC_IRQHandler                   [WEAK]
-                EXPORT  EXTI0_IRQHandler                 [WEAK]
-                EXPORT  EXTI1_IRQHandler                 [WEAK]
-                EXPORT  EXTI2_IRQHandler                 [WEAK]
-                EXPORT  EXTI3_IRQHandler                 [WEAK]
-                EXPORT  EXTI4_IRQHandler                 [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
-                EXPORT  ADC1_IRQHandler                  [WEAK]
-                EXPORT  EXTI9_5_IRQHandler               [WEAK]
-                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler               [WEAK]
-                EXPORT  TIM2_IRQHandler                  [WEAK]
-                EXPORT  TIM3_IRQHandler                  [WEAK]
-                EXPORT  TIM4_IRQHandler                  [WEAK]
-                EXPORT  I2C1_EV_IRQHandler               [WEAK]
-                EXPORT  I2C1_ER_IRQHandler               [WEAK]
-                EXPORT  I2C2_EV_IRQHandler               [WEAK]
-                EXPORT  I2C2_ER_IRQHandler               [WEAK]
-                EXPORT  SPI1_IRQHandler                  [WEAK]
-                EXPORT  SPI2_IRQHandler                  [WEAK]
-                EXPORT  USART1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler                [WEAK]
-                EXPORT  USART3_IRQHandler                [WEAK]
-                EXPORT  EXTI15_10_IRQHandler             [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler             [WEAK]
-                EXPORT  CEC_IRQHandler                   [WEAK]
-                EXPORT  TIM12_IRQHandler                 [WEAK]
-                EXPORT  TIM13_IRQHandler                 [WEAK]
-                EXPORT  TIM14_IRQHandler                 [WEAK]
-                EXPORT  TIM5_IRQHandler                  [WEAK]
-                EXPORT  SPI3_IRQHandler                  [WEAK]
-                EXPORT  UART4_IRQHandler                 [WEAK]
-                EXPORT  UART5_IRQHandler                 [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
-                EXPORT  TIM7_IRQHandler                  [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler         [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler         [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler         [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler       [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler         [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM15_IRQHandler
-TIM1_UP_TIM16_IRQHandler
-TIM1_TRG_COM_TIM17_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-CEC_IRQHandler
-TIM12_IRQHandler
-TIM13_IRQHandler
-TIM14_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-DMA2_Channel5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101x6.s

@@ -1,276 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f101x6.s
-;* Author             : MCD Application Team
-;* Description        : STM32F101x6 Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler            ; ADC1
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     0                          ; Reserved
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     0                          ; Reserved
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     0                          ; Reserved
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]            
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xb.s

@@ -1,286 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f101xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32F101xB Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler            ; ADC1
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xe.s

@@ -1,324 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f101xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32F101xE Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler            ; ADC1
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     FSMC_IRQHandler            ; FSMC
-                DCD     0                          ; Reserved
-                DCD     TIM5_IRQHandler            ; TIM5
-                DCD     SPI3_IRQHandler            ; SPI3
-                DCD     UART4_IRQHandler           ; UART4
-                DCD     UART5_IRQHandler           ; UART5
-                DCD     TIM6_IRQHandler            ; TIM6
-                DCD     TIM7_IRQHandler            ; TIM7
-                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0               
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  FSMC_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-FSMC_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xg.s

@@ -1,336 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f101xg.s
-;* Author             : MCD Application Team
-;* Description        : STM32F101xG Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler               ; Window Watchdog
-                DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler             ; Tamper
-                DCD     RTC_IRQHandler                ; RTC
-                DCD     FLASH_IRQHandler              ; Flash
-                DCD     RCC_IRQHandler                ; RCC
-                DCD     EXTI0_IRQHandler              ; EXTI Line 0
-                DCD     EXTI1_IRQHandler              ; EXTI Line 1
-                DCD     EXTI2_IRQHandler              ; EXTI Line 2
-                DCD     EXTI3_IRQHandler              ; EXTI Line 3
-                DCD     EXTI4_IRQHandler              ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler               ; ADC1
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
-                DCD     TIM9_IRQHandler               ; TIM9
-                DCD     TIM10_IRQHandler              ; TIM10
-                DCD     TIM11_IRQHandler              ; TIM11
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler               ; TIM2
-                DCD     TIM3_IRQHandler               ; TIM3
-                DCD     TIM4_IRQHandler               ; TIM4
-                DCD     I2C1_EV_IRQHandler            ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler            ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler            ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler            ; I2C2 Error
-                DCD     SPI1_IRQHandler               ; SPI1
-                DCD     SPI2_IRQHandler               ; SPI2
-                DCD     USART1_IRQHandler             ; USART1
-                DCD     USART2_IRQHandler             ; USART2
-                DCD     USART3_IRQHandler             ; USART3
-                DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler           ; RTC Alarm through EXTI Line
-                DCD     0                          ; Reserved
-                DCD     TIM12_IRQHandler                ; TIM12
-                DCD     TIM13_IRQHandler                ; TIM13 
-                DCD     TIM14_IRQHandler                ; TIM14
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     FSMC_IRQHandler               ; FSMC
-                DCD     0                          ; Reserved
-                DCD     TIM5_IRQHandler               ; TIM5
-                DCD     SPI3_IRQHandler               ; SPI3
-                DCD     UART4_IRQHandler              ; UART4
-                DCD     UART5_IRQHandler              ; UART5
-                DCD     TIM6_IRQHandler               ; TIM6
-                DCD     TIM7_IRQHandler               ; TIM7
-                DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0               
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler               [WEAK]
-                EXPORT  PVD_IRQHandler                [WEAK]
-                EXPORT  TAMPER_IRQHandler             [WEAK]
-                EXPORT  RTC_IRQHandler                [WEAK]
-                EXPORT  FLASH_IRQHandler              [WEAK]
-                EXPORT  RCC_IRQHandler                [WEAK]
-                EXPORT  EXTI0_IRQHandler              [WEAK]
-                EXPORT  EXTI1_IRQHandler              [WEAK]
-                EXPORT  EXTI2_IRQHandler              [WEAK]
-                EXPORT  EXTI3_IRQHandler              [WEAK]
-                EXPORT  EXTI4_IRQHandler              [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler      [WEAK]
-                EXPORT  ADC1_IRQHandler               [WEAK]
-                EXPORT  EXTI9_5_IRQHandler            [WEAK]
-                EXPORT  TIM9_IRQHandler               [WEAK]
-                EXPORT  TIM10_IRQHandler              [WEAK]
-                EXPORT  TIM11_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler               [WEAK]
-                EXPORT  TIM3_IRQHandler               [WEAK]
-                EXPORT  TIM4_IRQHandler               [WEAK]
-                EXPORT  I2C1_EV_IRQHandler            [WEAK]
-                EXPORT  I2C1_ER_IRQHandler            [WEAK]
-                EXPORT  I2C2_EV_IRQHandler            [WEAK]
-                EXPORT  I2C2_ER_IRQHandler            [WEAK]
-                EXPORT  SPI1_IRQHandler               [WEAK]
-                EXPORT  SPI2_IRQHandler               [WEAK]
-                EXPORT  USART1_IRQHandler             [WEAK]
-                EXPORT  USART2_IRQHandler             [WEAK]
-                EXPORT  USART3_IRQHandler             [WEAK]
-                EXPORT  EXTI15_10_IRQHandler          [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler          [WEAK]
-                EXPORT  TIM12_IRQHandler              [WEAK]
-                EXPORT  TIM13_IRQHandler              [WEAK]
-                EXPORT  TIM14_IRQHandler              [WEAK]
-                EXPORT  FSMC_IRQHandler               [WEAK]
-                EXPORT  TIM5_IRQHandler               [WEAK]
-                EXPORT  SPI3_IRQHandler               [WEAK]
-                EXPORT  UART4_IRQHandler              [WEAK]
-                EXPORT  UART5_IRQHandler              [WEAK]
-                EXPORT  TIM6_IRQHandler               [WEAK]
-                EXPORT  TIM7_IRQHandler               [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler    [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-TIM12_IRQHandler
-TIM13_IRQHandler
-TIM14_IRQHandler
-FSMC_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f102x6.s

@@ -1,283 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f102x6.s
-;* Author             : MCD Application Team
-;* Description        : STM32F102x6 Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler            ; ADC1
-                DCD     USB_HP_IRQHandler          ; USB High Priority
-                DCD     USB_LP_IRQHandler          ; USB Low  Priority
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     0                          ; Reserved
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     0                          ; Reserved
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     0                          ; Reserved
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-EXTI9_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f102xb.s

@@ -1,293 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f102xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32F102xB Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler            ; ADC1
-                DCD     USB_HP_IRQHandler          ; USB High Priority
-                DCD     USB_LP_IRQHandler          ; USB Low  Priority
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-EXTI9_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103x6.s

@@ -1,295 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f103x6.s
-;* Author             : MCD Application Team
-;* Description        : STM32F103x6 Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1_2
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     0                          ; Reserved
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     0                          ; Reserved
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     0                          ; Reserved
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xb.s

@@ -1,305 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f103xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32F103xB Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1_2
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xe.s

@@ -1,354 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f103xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32F103xE Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1 & ADC2
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-                DCD     TIM8_BRK_IRQHandler        ; TIM8 Break
-                DCD     TIM8_UP_IRQHandler         ; TIM8 Update
-                DCD     TIM8_TRG_COM_IRQHandler    ; TIM8 Trigger and Commutation
-                DCD     TIM8_CC_IRQHandler         ; TIM8 Capture Compare
-                DCD     ADC3_IRQHandler            ; ADC3
-                DCD     FSMC_IRQHandler            ; FSMC
-                DCD     SDIO_IRQHandler            ; SDIO
-                DCD     TIM5_IRQHandler            ; TIM5
-                DCD     SPI3_IRQHandler            ; SPI3
-                DCD     UART4_IRQHandler           ; UART4
-                DCD     UART5_IRQHandler           ; UART5
-                DCD     TIM6_IRQHandler            ; TIM6
-                DCD     TIM7_IRQHandler            ; TIM7
-                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0               
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-                EXPORT  TIM8_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM8_UP_IRQHandler         [WEAK]
-                EXPORT  TIM8_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM8_CC_IRQHandler         [WEAK]
-                EXPORT  ADC3_IRQHandler            [WEAK]
-                EXPORT  FSMC_IRQHandler            [WEAK]
-                EXPORT  SDIO_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-TIM8_BRK_IRQHandler
-TIM8_UP_IRQHandler
-TIM8_TRG_COM_IRQHandler
-TIM8_CC_IRQHandler
-ADC3_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xg.s

@@ -1,354 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f103xg.s
-;* Author             : MCD Application Team
-;* Description        : STM32F103xG Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler               ; Window Watchdog
-                DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler             ; Tamper
-                DCD     RTC_IRQHandler                ; RTC
-                DCD     FLASH_IRQHandler              ; Flash
-                DCD     RCC_IRQHandler                ; RCC
-                DCD     EXTI0_IRQHandler              ; EXTI Line 0
-                DCD     EXTI1_IRQHandler              ; EXTI Line 1
-                DCD     EXTI2_IRQHandler              ; EXTI Line 2
-                DCD     EXTI3_IRQHandler              ; EXTI Line 3
-                DCD     EXTI4_IRQHandler              ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler             ; ADC1 & ADC2
-                DCD     USB_HP_CAN1_TX_IRQHandler     ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler    ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler           ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler           ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
-                DCD     TIM1_BRK_TIM9_IRQHandler      ; TIM1 Break and TIM9
-                DCD     TIM1_UP_TIM10_IRQHandler      ; TIM1 Update and TIM10
-                DCD     TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
-                DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler               ; TIM2
-                DCD     TIM3_IRQHandler               ; TIM3
-                DCD     TIM4_IRQHandler               ; TIM4
-                DCD     I2C1_EV_IRQHandler            ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler            ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler            ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler            ; I2C2 Error
-                DCD     SPI1_IRQHandler               ; SPI1
-                DCD     SPI2_IRQHandler               ; SPI2
-                DCD     USART1_IRQHandler             ; USART1
-                DCD     USART2_IRQHandler             ; USART2
-                DCD     USART3_IRQHandler             ; USART3
-                DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler           ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler          ; USB Wakeup from suspend
-                DCD     TIM8_BRK_TIM12_IRQHandler     ; TIM8 Break and TIM12
-                DCD     TIM8_UP_TIM13_IRQHandler      ; TIM8 Update and TIM13
-                DCD     TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
-                DCD     TIM8_CC_IRQHandler            ; TIM8 Capture Compare
-                DCD     ADC3_IRQHandler               ; ADC3
-                DCD     FSMC_IRQHandler               ; FSMC
-                DCD     SDIO_IRQHandler               ; SDIO
-                DCD     TIM5_IRQHandler               ; TIM5
-                DCD     SPI3_IRQHandler               ; SPI3
-                DCD     UART4_IRQHandler              ; UART4
-                DCD     UART5_IRQHandler              ; UART5
-                DCD     TIM6_IRQHandler               ; TIM6
-                DCD     TIM7_IRQHandler               ; TIM7
-                DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0               
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler               [WEAK]
-                EXPORT  PVD_IRQHandler                [WEAK]
-                EXPORT  TAMPER_IRQHandler             [WEAK]
-                EXPORT  RTC_IRQHandler                [WEAK]
-                EXPORT  FLASH_IRQHandler              [WEAK]
-                EXPORT  RCC_IRQHandler                [WEAK]
-                EXPORT  EXTI0_IRQHandler              [WEAK]
-                EXPORT  EXTI1_IRQHandler              [WEAK]
-                EXPORT  EXTI2_IRQHandler              [WEAK]
-                EXPORT  EXTI3_IRQHandler              [WEAK]
-                EXPORT  EXTI4_IRQHandler              [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler      [WEAK]
-                EXPORT  ADC1_2_IRQHandler             [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler     [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler    [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler           [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler           [WEAK]
-                EXPORT  EXTI9_5_IRQHandler            [WEAK]
-                EXPORT  TIM1_BRK_TIM9_IRQHandler      [WEAK]
-                EXPORT  TIM1_UP_TIM10_IRQHandler      [WEAK]
-                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
-                EXPORT  TIM1_CC_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler               [WEAK]
-                EXPORT  TIM3_IRQHandler               [WEAK]
-                EXPORT  TIM4_IRQHandler               [WEAK]
-                EXPORT  I2C1_EV_IRQHandler            [WEAK]
-                EXPORT  I2C1_ER_IRQHandler            [WEAK]
-                EXPORT  I2C2_EV_IRQHandler            [WEAK]
-                EXPORT  I2C2_ER_IRQHandler            [WEAK]
-                EXPORT  SPI1_IRQHandler               [WEAK]
-                EXPORT  SPI2_IRQHandler               [WEAK]
-                EXPORT  USART1_IRQHandler             [WEAK]
-                EXPORT  USART2_IRQHandler             [WEAK]
-                EXPORT  USART3_IRQHandler             [WEAK]
-                EXPORT  EXTI15_10_IRQHandler          [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler           [WEAK]
-                EXPORT  USBWakeUp_IRQHandler          [WEAK]
-                EXPORT  TIM8_BRK_TIM12_IRQHandler     [WEAK]
-                EXPORT  TIM8_UP_TIM13_IRQHandler      [WEAK]
-                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
-                EXPORT  TIM8_CC_IRQHandler            [WEAK]
-                EXPORT  ADC3_IRQHandler               [WEAK]
-                EXPORT  FSMC_IRQHandler               [WEAK]
-                EXPORT  SDIO_IRQHandler               [WEAK]
-                EXPORT  TIM5_IRQHandler               [WEAK]
-                EXPORT  SPI3_IRQHandler               [WEAK]
-                EXPORT  UART4_IRQHandler              [WEAK]
-                EXPORT  UART5_IRQHandler              [WEAK]
-                EXPORT  TIM6_IRQHandler               [WEAK]
-                EXPORT  TIM7_IRQHandler               [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler    [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-ADC3_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f105xc.s

@@ -1,362 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f105xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32F105xC Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1 and ADC2
-                DCD     CAN1_TX_IRQHandler         ; CAN1 TX
-                DCD     CAN1_RX0_IRQHandler        ; CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C1 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC alarm through EXTI line
-                DCD     OTG_FS_WKUP_IRQHandler     ; USB OTG FS Wakeup through EXTI line
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM5_IRQHandler            ; TIM5
-                DCD     SPI3_IRQHandler            ; SPI3
-                DCD     UART4_IRQHandler           ; UART4
-                DCD     UART5_IRQHandler           ; UART5
-                DCD     TIM6_IRQHandler            ; TIM6
-                DCD     TIM7_IRQHandler            ; TIM7
-                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
-                DCD     DMA2_Channel4_IRQHandler   ; DMA2 Channel4
-                DCD     DMA2_Channel5_IRQHandler   ; DMA2 Channel5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     CAN2_TX_IRQHandler         ; CAN2 TX
-                DCD     CAN2_RX0_IRQHandler        ; CAN2 RX0
-                DCD     CAN2_RX1_IRQHandler        ; CAN2 RX1
-                DCD     CAN2_SCE_IRQHandler        ; CAN2 SCE
-                DCD     OTG_FS_IRQHandler          ; USB OTG FS
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  CAN1_TX_IRQHandler         [WEAK]
-                EXPORT  CAN1_RX0_IRQHandler        [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  OTG_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  CAN2_TX_IRQHandler         [WEAK]
-                EXPORT  CAN2_RX0_IRQHandler        [WEAK]
-                EXPORT  CAN2_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN2_SCE_IRQHandler        [WEAK]
-                EXPORT  OTG_FS_IRQHandler          [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f107xc.s

@@ -1,366 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f107xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32F107xC Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1 and ADC2
-                DCD     CAN1_TX_IRQHandler         ; CAN1 TX
-                DCD     CAN1_RX0_IRQHandler        ; CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C1 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC alarm through EXTI line
-                DCD     OTG_FS_WKUP_IRQHandler     ; USB OTG FS Wakeup through EXTI line
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM5_IRQHandler            ; TIM5
-                DCD     SPI3_IRQHandler            ; SPI3
-                DCD     UART4_IRQHandler           ; UART4
-                DCD     UART5_IRQHandler           ; UART5
-                DCD     TIM6_IRQHandler            ; TIM6
-                DCD     TIM7_IRQHandler            ; TIM7
-                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
-                DCD     DMA2_Channel4_IRQHandler   ; DMA2 Channel4
-                DCD     DMA2_Channel5_IRQHandler   ; DMA2 Channel5
-                DCD     ETH_IRQHandler             ; Ethernet
-                DCD     ETH_WKUP_IRQHandler        ; Ethernet Wakeup through EXTI line
-                DCD     CAN2_TX_IRQHandler         ; CAN2 TX
-                DCD     CAN2_RX0_IRQHandler        ; CAN2 RX0
-                DCD     CAN2_RX1_IRQHandler        ; CAN2 RX1
-                DCD     CAN2_SCE_IRQHandler        ; CAN2 SCE
-                DCD     OTG_FS_IRQHandler          ; USB OTG FS
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  CAN1_TX_IRQHandler         [WEAK]
-                EXPORT  CAN1_RX0_IRQHandler        [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  OTG_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  ETH_IRQHandler             [WEAK]
-                EXPORT  ETH_WKUP_IRQHandler        [WEAK]
-                EXPORT  CAN2_TX_IRQHandler         [WEAK]
-                EXPORT  CAN2_RX0_IRQHandler        [WEAK]
-                EXPORT  CAN2_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN2_SCE_IRQHandler        [WEAK]
-                EXPORT  OTG_FS_IRQHandler          [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f100xb.s

@@ -1,407 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f100xb.s
-  * @author    MCD Application Team
-  * @brief     STM32F100xB Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_TIM15_IRQHandler
-  .word TIM1_UP_TIM16_IRQHandler
-  .word TIM1_TRG_COM_TIM17_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word CEC_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM6_DAC_IRQHandler
-  .word TIM7_IRQHandler  
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x01CC. This is for boot in RAM mode for 
-                            STM32F10xB Value Line devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM15_IRQHandler
-  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM16_IRQHandler
-  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM17_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-  
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-  
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-  
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-  
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak  CEC_IRQHandler
-  .thumb_set CEC_IRQHandler,Default_Handler
-
-  .weak  TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler  
-
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f100xe.s

@@ -1,449 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f100xe.s
-  * @author    MCD Application Team
-  * @brief     STM32F100xE Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_TIM15_IRQHandler
-  .word TIM1_UP_TIM16_IRQHandler
-  .word TIM1_TRG_COM_TIM17_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word CEC_IRQHandler
-  .word TIM12_IRQHandler
-  .word TIM13_IRQHandler
-  .word TIM14_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_DAC_IRQHandler
-  .word TIM7_IRQHandler  
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_5_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x High Density Value line devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM15_IRQHandler
-  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM16_IRQHandler
-  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM17_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak  CEC_IRQHandler
-  .thumb_set CEC_IRQHandler,Default_Handler
-
-  .weak  TIM12_IRQHandler
-  .thumb_set TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM13_IRQHandler
-  .thumb_set TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM14_IRQHandler
-  .thumb_set TIM14_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak  TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler 
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler  
-
-  .weak  DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f101x6.s

@@ -1,322 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f101x6.s
-  * @author    MCD Application Team
-  * @brief     STM32F101x6 Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word 0
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word 0
-  .word 0
-  .word SPI1_IRQHandler
-  .word 0
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word 0
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM        /* @0x108. This is for boot in RAM mode for
-                          STM32F10x Low Density devices.*/
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f101xb.s

@@ -1,338 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f101xb.s
-  * @author    MCD Application Team
-  * @brief     STM32F101xB Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for
-                            STM32F10x Medium Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f101xe.s

@@ -1,423 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f101xe.s
-  * @author    MCD Application Team
-  * @brief     STM32F101xE Value Line Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word FSMC_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM       /* @0x1E0. This is for boot in RAM mode for
-                         STM32F10x High Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f101xg.s

@@ -1,439 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f101xg.s
-  * @author    MCD Application Team
-  * @brief     STM32F101xG Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None
- * @retval None       
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  EXTI9_5_IRQHandler
-  .word  TIM9_IRQHandler
-  .word  TIM10_IRQHandler
-  .word  TIM11_IRQHandler
-  .word  0
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTC_Alarm_IRQHandler
-  .word 0
-  .word TIM12_IRQHandler
-  .word TIM13_IRQHandler
-  .word TIM14_IRQHandler
-  .word 0
-  .word 0
-  .word  FSMC_IRQHandler
-  .word 0
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_IRQHandler
-  .word  TIM7_IRQHandler
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_5_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x XL-Density devices. */
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-* 
-*******************************************************************************/
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak  TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak  TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak  TIM12_IRQHandler
-  .thumb_set TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM13_IRQHandler
-  .thumb_set TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM14_IRQHandler
-  .thumb_set TIM14_IRQHandler,Default_Handler
-
-  .weak  FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f102x6.s

@@ -1,330 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f102x6.s
-  * @author    MCD Application Team
-  * @brief     STM32F102x6 Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word 0 
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word 0
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word 0
-  .word 0
-  .word SPI1_IRQHandler
-  .word 0
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word 0
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USBWakeUp_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM        /* @0x108. This is for boot in RAM mode for
-                          STM32F10x Low Density devices.*/
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f102xb.s

@@ -1,346 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f102xb.s
-  * @author    MCD Application Team
-  * @brief     STM32F102xB Value Line Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word 0 
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USBWakeUp_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for
-                            STM32F10x Medium Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103x6.s

@@ -1,348 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f103x6.s
-  * @author    MCD Application Team
-  * @brief     STM32F103x6 Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_2_IRQHandler
-  .word USB_HP_CAN1_TX_IRQHandler
-  .word USB_LP_CAN1_RX0_IRQHandler
-  .word CAN1_RX1_IRQHandler
-  .word CAN1_SCE_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_IRQHandler
-  .word TIM1_UP_IRQHandler
-  .word TIM1_TRG_COM_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word 0
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word 0
-  .word 0
-  .word SPI1_IRQHandler
-  .word 0
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word 0
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USBWakeUp_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM        /* @0x108. This is for boot in RAM mode for
-                          STM32F10x Low Density devices.*/
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak USB_HP_CAN1_TX_IRQHandler
-  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-  .weak USB_LP_CAN1_RX0_IRQHandler
-  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM1_BRK_IRQHandler
-  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-  .weak TIM1_UP_IRQHandler
-  .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-  .weak TIM1_TRG_COM_IRQHandler
-  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-  .weak TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xe.s

@@ -1,470 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f103xe.s
-  * @author    MCD Application Team
-  * @brief     STM32F103xE Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Configure external SRAM mounted on STM3210E-EVAL board
-  *                  to be used as data memory (optional, to be enabled by user)
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_2_IRQHandler
-  .word USB_HP_CAN1_TX_IRQHandler
-  .word USB_LP_CAN1_RX0_IRQHandler
-  .word CAN1_RX1_IRQHandler
-  .word CAN1_SCE_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_IRQHandler
-  .word TIM1_UP_IRQHandler
-  .word TIM1_TRG_COM_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USBWakeUp_IRQHandler
-  .word TIM8_BRK_IRQHandler
-  .word TIM8_UP_IRQHandler
-  .word TIM8_TRG_COM_IRQHandler
-  .word TIM8_CC_IRQHandler
-  .word ADC3_IRQHandler
-  .word FSMC_IRQHandler
-  .word SDIO_IRQHandler
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM       /* @0x1E0. This is for boot in RAM mode for
-                         STM32F10x High Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak USB_HP_CAN1_TX_IRQHandler
-  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-  .weak USB_LP_CAN1_RX0_IRQHandler
-  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM1_BRK_IRQHandler
-  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-  .weak TIM1_UP_IRQHandler
-  .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-  .weak TIM1_TRG_COM_IRQHandler
-  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-  .weak TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-  .weak TIM8_BRK_IRQHandler
-  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
-
-  .weak TIM8_UP_IRQHandler
-  .thumb_set TIM8_UP_IRQHandler,Default_Handler
-
-  .weak TIM8_TRG_COM_IRQHandler
-  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
-
-  .weak TIM8_CC_IRQHandler
-  .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-  .weak ADC3_IRQHandler
-  .thumb_set ADC3_IRQHandler,Default_Handler
-
-  .weak FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xg.s

@@ -1,466 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f103xb.s
-  * @author    MCD Application Team
-  * @brief     STM32F103xB Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None
- * @retval None       
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_2_IRQHandler
-  .word  USB_HP_CAN1_TX_IRQHandler
-  .word  USB_LP_CAN1_RX0_IRQHandler
-  .word  CAN1_RX1_IRQHandler
-  .word  CAN1_SCE_IRQHandler
-  .word  EXTI9_5_IRQHandler
-  .word  TIM1_BRK_TIM9_IRQHandler
-  .word  TIM1_UP_TIM10_IRQHandler
-  .word  TIM1_TRG_COM_TIM11_IRQHandler
-  .word  TIM1_CC_IRQHandler
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTC_Alarm_IRQHandler
-  .word  USBWakeUp_IRQHandler
-  .word  TIM8_BRK_TIM12_IRQHandler
-  .word  TIM8_UP_TIM13_IRQHandler
-  .word  TIM8_TRG_COM_TIM14_IRQHandler
-  .word  TIM8_CC_IRQHandler
-  .word  ADC3_IRQHandler
-  .word  FSMC_IRQHandler
-  .word  SDIO_IRQHandler
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_IRQHandler
-  .word  TIM7_IRQHandler
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_5_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x XL-Density devices. */
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-* 
-*******************************************************************************/
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak  USB_HP_CAN1_TX_IRQHandler
-  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-  .weak  USB_LP_CAN1_RX0_IRQHandler
-  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM9_IRQHandler
-  .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM10_IRQHandler
-  .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM11_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak  USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-  .weak  TIM8_BRK_TIM12_IRQHandler
-  .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM8_UP_TIM13_IRQHandler
-  .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM8_TRG_COM_TIM14_IRQHandler
-  .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
-  .weak  TIM8_CC_IRQHandler
-  .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-  .weak  ADC3_IRQHandler
-  .thumb_set ADC3_IRQHandler,Default_Handler
-
-  .weak  FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak  SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f105xc.s

@@ -1,463 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f105xc.s
-  * @author    MCD Application Team
-  * @brief     STM32F105xC Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None
- * @retval None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_2_IRQHandler
-  .word CAN1_TX_IRQHandler
-  .word CAN1_RX0_IRQHandler
-   .word CAN1_RX1_IRQHandler
-  .word CAN1_SCE_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_IRQHandler
-  .word TIM1_UP_IRQHandler
-  .word TIM1_TRG_COM_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word OTG_FS_WKUP_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word 0
-  .word CAN2_TX_IRQHandler
-  .word CAN2_RX0_IRQHandler
-  .word CAN2_RX1_IRQHandler
-  .word CAN2_SCE_IRQHandler
-  .word OTG_FS_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM     /* @0x1E0. This is for boot in RAM mode for
-                         STM32F10x Connectivity line Devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak CAN1_TX_IRQHandler
-  .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
-  .weak CAN1_RX0_IRQHandler
-  .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM1_BRK_IRQHandler
-  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-  .weak TIM1_UP_IRQHandler
-  .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-  .weak TIM1_TRG_COM_IRQHandler
-  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-  .weak TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak OTG_FS_WKUP_IRQHandler
-  .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak CAN2_TX_IRQHandler
-  .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
-  .weak CAN2_RX0_IRQHandler
-  .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
-  .weak CAN2_RX1_IRQHandler
-  .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
-  .weak CAN2_SCE_IRQHandler
-  .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
-  .weak OTG_FS_IRQHandler
-  .thumb_set OTG_FS_IRQHandler ,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f107xc.s

@@ -1,472 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f107xc.s
-  * @author    MCD Application Team
-  * @brief     STM32F107xC Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_2_IRQHandler
-  .word CAN1_TX_IRQHandler
-  .word CAN1_RX0_IRQHandler
-  .word CAN1_RX1_IRQHandler
-  .word CAN1_SCE_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_IRQHandler
-  .word TIM1_UP_IRQHandler
-  .word TIM1_TRG_COM_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word OTG_FS_WKUP_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word ETH_IRQHandler
-  .word ETH_WKUP_IRQHandler
-  .word CAN2_TX_IRQHandler
-  .word CAN2_RX0_IRQHandler
-  .word CAN2_RX1_IRQHandler
-  .word CAN2_SCE_IRQHandler
-  .word OTG_FS_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM     /* @0x1E0. This is for boot in RAM mode for
-                         STM32F10x Connectivity line Devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak  CAN1_TX_IRQHandler
-  .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX0_IRQHandler
-  .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_IRQHandler
-  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_IRQHandler
-  .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_IRQHandler
-  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak  OTG_FS_WKUP_IRQHandler
-  .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak  ETH_IRQHandler
-  .thumb_set ETH_IRQHandler,Default_Handler
-
-  .weak  ETH_WKUP_IRQHandler
-  .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
-  .weak  CAN2_TX_IRQHandler
-  .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
-  .weak  CAN2_RX0_IRQHandler
-  .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN2_RX1_IRQHandler
-  .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN2_SCE_IRQHandler
-  .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
-  .weak  OTG_FS_IRQHandler
-  .thumb_set OTG_FS_IRQHandler ,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f100xb_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20001FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f100xb_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20001FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f100xe_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f100xe_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101x6_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x08007FFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x200017FF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101x6_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x200017FF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101xb_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101xb_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101xe_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101xe_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101xg_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20013FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101xg_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20013FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f102x6_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x08007FFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x200017FF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f102x6_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x200017FF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f102xb_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f102xb_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103x6_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x08007FFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x200027FF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103x6_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x200027FF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103xb_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20004FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103xb_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20004FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103xe_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x2000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103xe_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x2000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103xg_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f103xg_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f105xc_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x2000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f105xc_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x2000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f107xc_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x2000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };