feat(ch390): optimize SPI transfer, MAC fallback, and build settings for V1.0.0

- increase UART DMA/ring buffer sizes for mux traffic
- switch SPI1 to Mode0 with prescaler /2 and align CubeMX settings
- refactor CH390 memory read/write path with chunked SPI read and HAL bulk write
- fallback to hardware MAC when configured MAC is invalid (all-zero)
- add mux frame RTT logs and remove redundant UART1 polling
- update Keil post-build viewer integration and include build viewer artifacts
- update AT manual with all-zero MAC behavior

.debug/uart-ch390-debug-handoff.md

@@ -0,0 +1,174 @@
+# TCP2UART Debug Handoff
+
+## Scope
+
+This log records the debugging work completed so far for:
+
+- UART1 config/debug path on `COM9`
+- UART2/UART3 transparent UART paths on `COM8`/`COM7`
+- CH390 and lwIP bring-up status
+
+The goal is to preserve the usable conclusions and avoid repeating invalid test paths after context cleanup.
+
+## Final State Summary
+
+### Confirmed working
+
+- HSE clock path is working on the current board/chip/crystal combination.
+- ST-Link + RTT debugging works.
+- Firmware boots and RTT shows stable startup output.
+- UART2 and UART3 TX paths were validated earlier by host-side observation:
+  - `COM8` receives UART2 debug output.
+  - `COM7` receives UART3 debug output.
+- UART1 config path is working in the current cleaned firmware when the host sends commands with a line ending that the parser actually consumes.
+- `AT+?` over UART1 was successfully validated when sent with `\n`.
+
+### Confirmed not yet working
+
+- CH390 is still not operating normally.
+- Current one-shot RTT report still shows abnormal values:
+  - `CH390 VID=0x3A3A PID=0xCCCC REV=0x00 NSR=0x00 LINK=0`
+- Therefore lwIP / Ethernet / TCP end-to-end validation remains blocked by CH390 low-level failure.
+
+## Most Important Lessons Learned
+
+### 1. UART1 config failures were partly test-method failures
+
+Several earlier negative conclusions about UART1 config were caused by the debug method rather than firmware defects.
+
+Examples:
+
+- Sending `AT+?` without the line ending expected by the current parser caused false negatives.
+- Frequent open/close cycles on the serial port changed timing and control-line behavior.
+- Breakpoints in RX callback / parser code prevented reply transmission and created false "no response" results.
+- Heavy RTT logging inside hot UART paths distorted timing and even corrupted RTT control state once.
+
+### 2. UART1 parser expects terminators
+
+`config_uart_rx_byte()` only dispatches a command when it sees `\r` or `\n`.
+
+Successful command form that was confirmed:
+
+```text
+AT+?\n
+```
+
+Do not assume `AT+?` without line ending is valid for this firmware.
+
+### 3. Cleaned firmware state is preferable for future work
+
+Temporary UART diagnostics were removed again after debugging:
+
+- removed boot markers like `BOOT_UARTx_OK`
+- removed periodic UART spam
+- removed UART1 byte echo
+- removed temporary `config_diag` counters
+
+Useful RTT remains:
+
+- `TCP2UART boot`
+- HSE fallback warning if used
+- CH390 one-shot status report
+
+## Relevant Code Changes Left In Place
+
+These are intentional and should remain unless there is a specific reason to change them.
+
+### UART1 config path
+
+- `App/config.c`
+  - config handle is back on `huart1`
+  - `config_uart_rx_byte()` assembles frames from UART1 bytes
+  - `config_poll()` dispatches a pending complete frame to `config_try_process_frame()`
+  - `config_try_process_frame()` calls `config_process_at_cmd()` and transmits the response on UART1
+
+- `Core/Src/stm32f1xx_it.c`
+  - `HAL_UART_RxCpltCallback()` for `huart1` feeds the received byte into `config_uart_rx_byte()` and rearms `HAL_UART_Receive_IT()`
+
+### RTT boot diagnostics
+
+- `Core/Src/main.c`
+  - retains RTT boot banner
+  - retains one-shot CH390 report
+  - no temporary UART spam remains
+
+## Current Firmware Behavior Worth Remembering
+
+### UART1
+
+- UART1 is used for config/debug interaction.
+- UART1 parser is line-oriented.
+- Use a terminal that sends `LF` or `CRLF` explicitly.
+
+### UART2 / UART3
+
+- UART2 and UART3 are for bridge channels, not the config path.
+- Earlier mapping observed during testing:
+  - `COM8` aligned with UART2 TX activity
+  - `COM7` aligned with UART3 TX activity
+
+### CH390
+
+- Still unresolved at the low level.
+- Do not spend time on lwIP / TCP behavior until CH390 register reads look sane.
+
+## Recommended Next Debug Order
+
+### Priority 1: Preserve UART1 config as known-good
+
+Before touching UART1 code again:
+
+1. Open `COM9` at `115200 8N1`
+2. Send:
+
+```text
+AT+?\n
+```
+
+3. Confirm a full config dump is returned.
+
+If this fails again, check the terminal's actual line ending first before changing code.
+
+### Priority 2: Re-verify UART2/UART3 only if needed
+
+If bridge debugging resumes, first confirm the host can actually open `COM7` and `COM8`.
+Host-side availability was inconsistent during the previous session and caused false negatives.
+
+### Priority 3: Resume CH390 low-level debugging
+
+This is the real remaining blocker.
+
+Suggested next steps:
+
+1. Focus on SPI-level sanity before lwIP.
+2. Re-check CH390 reset / CS / SPI timing and electrical path.
+3. Verify whether SPI mode is correct for the actual hardware.
+4. Confirm register reads from CH390 return plausible values before attempting link/TCP tests.
+
+## What Not To Repeat
+
+- Do not judge UART1 config by sending commands without a terminator.
+- Do not leave breakpoints inside UART RX callback or parser while expecting normal replies.
+- Do not flood RTT inside hot UART receive paths.
+- Do not conclude lwIP is broken before CH390 identity reads are sane.
+- Do not trust `Win32_SerialPort` alone for COM availability; sometimes `mode COMx` / `Get-PnpDevice -Class Ports` gives a different picture.
+
+## Known Useful Commands
+
+### UART1 config test
+
+```text
+AT+?\n
+```
+
+### Optional follow-ups
+
+```text
+AT+BAUD1=115200\n
+AT+SAVE\n
+AT+RESET\n
+```
+
+## One-Line Handoff
+
+UART1 config is working when tested correctly with a terminator; CH390 is still the unresolved core issue and should be the next serious debug target.

.embeddedskills/config.json

@@ -1,7 +0,0 @@
-{
-  "keil": {
-    "project": "MDK-ARM/TCP2UART.uvprojx",
-    "target": "TCP2UART",
-    "log_dir": ".embeddedskills/build"
-  }
-}

.gitignore

@@ -7,6 +7,7 @@
 *.map
 *.lst
 *.out
+*.log
 
 # IDE
 .vscode/
@@ -26,18 +27,9 @@ Release/
 *.uvguix.*
 MDK-ARM/DebugConfig/
 MDK-ARM/TCP2UART/
-build_keil.log
+
-MDK-ARM/build.log
+# CMake build
-MDK-ARM/build_capture.txt
+build/
-MDK-ARM/build_output.txt
-MDK-ARM/keil-build-viewer.log
-MDK-ARM/keil-build-viewer-record.txt
-MDK-ARM/keil-build-viewer.exe
-MDK-ARM/EventRecorderStub.scvd
-.embeddedskills/build/
-.embeddedskills/state.json
-build_current.log
-uv4_stdout.txt
 
 # OS
 Thumbs.db
@@ -47,5 +39,8 @@ Desktop.ini
 # 项目文档
 项目计划.md
 
-# Wireshark
+# Local debug handoff logs
+.debug/
+
+# Local packet captures
 WiresharkLog/

AT固件使用手册.md

@@ -14,18 +14,11 @@
 
 ## 2. 设备与接口
 
-- 主控：`STM32F103RCT6`（256KB Flash / 48KB SRAM）
+- 主控：`STM32F103R8T6`
 - 以太网芯片：`CH390D`
 - 配置口：`USART1`
 - 数据口：`USART2`、`USART3`
 
-### 2.1 固件版本线
-
-- FreeRTOS + lwIP 版本线从 `V2.0.0` 开始。
-- 裸机版本线从 `V1.0.0` 开始。
-- 当前 FreeRTOS 固件基线 release：`TCP2UART RTOS V2.0.0`。
-- 固件下载：`https://git.furtherverse.com/gaoro-xiao/TCP2UART/releases/tag/V2.0.0`
-
 职责划分：
 
 - `USART1`：AT 配置口
@@ -77,8 +70,8 @@ SYNC | LEN_H | LEN_L | SRCID | DSTMASK | PAYLOAD | TAIL
 |------|------|
 | `C1` | `0x01` |
 | `C2` | `0x02` |
-| `U0` | `0x04` |
+| `UART2` | `0x04` |
-| `U1` | `0x08` |
+| `UART3` | `0x08` |
 | `S1` | `0x10` |
 | `S2` | `0x20` |
 
@@ -99,7 +92,7 @@ SYNC | LEN_H | LEN_L | SRCID | DSTMASK | PAYLOAD | TAIL
 ```text
 AT\r\n
 AT+MUX?\r\n
-AT+NET=192.168.31.100,255.255.255.0,192.168.31.1,00:00:00:00:00:00\r\n
+AT+NET=192.168.1.100,255.255.255.0,192.168.1.1,02:00:00:00:00:01\r\n
 ```
 
 ### 6.2 持久化规则
@@ -128,11 +121,9 @@ MUX = 0
 ### 7.2 NET 默认值
 
 ```text
-NET = 192.168.31.100,255.255.255.0,192.168.31.1,00:00:00:00:00:00
+NET = 192.168.1.100,255.255.255.0,192.168.1.1,02:00:00:00:00:01
 ```
 
-默认 MAC 为全 0，表示 Flash 中不固化板卡 MAC；运行时使用 `CH390D` 内部 MAC。`AT+?` 与 `AT+NET?` 回显的是当前生效 MAC。
-
 ### 7.3 LINK 默认值
 
 ```text
@@ -180,7 +171,7 @@ AT+QUERY\r\n
 推荐返回格式：
 
 ```text
-+NET:IP=192.168.31.100,MASK=255.255.255.0,GW=192.168.31.1,MAC=<当前生效MAC>
++NET:IP=192.168.1.100,MASK=255.255.255.0,GW=192.168.1.1,MAC=02:00:00:00:00:01
 +LINK:S1,EN=1,LPORT=8080,RIP=0.0.0.0,RPORT=0,UART=U0
 +LINK:S2,EN=0,LPORT=8081,RIP=0.0.0.0,RPORT=0,UART=U1
 +LINK:C1,EN=1,LPORT=9001,RIP=192.168.1.200,RPORT=9000,UART=U1
@@ -222,7 +213,7 @@ OK
 #### 设置 NET
 
 ```text
-AT+NET=192.168.31.100,255.255.255.0,192.168.31.1,00:00:00:00:00:00\r\n
+AT+NET=192.168.1.100,255.255.255.0,192.168.1.1,02:00:00:00:00:01\r\n
 ```
 
 字段顺序：
@@ -240,13 +231,13 @@ AT+NET?\r\n
 返回示例：
 
 ```text
-+NET:IP=192.168.31.100,MASK=255.255.255.0,GW=192.168.31.1,MAC=<当前生效MAC>
++NET:IP=192.168.1.100,MASK=255.255.255.0,GW=192.168.1.1,MAC=02:00:00:00:00:01
 OK
 ```
 
 **MAC 设置说明：**
 
-当 MAC 设置为全 0 时，固件将使用 `CH390D` 内部 MAC 地址。此时 Flash 内仍保存全 0，不会把内部 MAC 写回 Flash；`AT+?` 和 `AT+NET?` 查询到的 MAC 地址为当前运行时生效的硬件 MAC 地址。
+当MAC设置为全0时，固件将使用硬件MAC地址，此时通过AT+?查询到的MAC地址即为当前生效的硬件MAC地址。
 
 ### 8.5 LINK 类命令
 
@@ -277,9 +268,6 @@ ROLE,EN,LPORT,RIP,RPORT,UART
 - `Server` 与 `Client` 共用同一条 `LINK` 记录模型
 - `Server` 中 `RIP/RPORT` 可作为允许接入的对端约束或预设对端信息
 - `Client` 中 `RIP/RPORT` 表示远端目标地址与端口
-- `Client` 侧当前保留固定 `LPORT` 语义，用于满足部分上位机或现场网络策略对固定源端口的依赖
-- 为避免固定 `LPORT` 下频繁重连被 lwIP `TIME_WAIT` 长时间占用阻塞，当前固件对 `Client` 主动断开后的释放路径采用 abortive close（RST）而非优雅 `FIN/ACK` 关闭
-- 因此 `Client` 重连场景下，对端可能观察到 `RST` 或“连接被重置”，这属于当前产品约束下的有意设计取舍，不影响 `AT+LINK` 对 `LPORT` 的配置语义
 
 #### 查询单条 LINK
 
@@ -366,7 +354,7 @@ OK: Defaults restored
 ## 11. 推荐配置流程
 
 ```text
-AT+NET=192.168.31.123,255.255.255.0,192.168.31.1,00:00:00:00:00:00\r\n
+AT+NET=192.168.1.123,255.255.255.0,192.168.1.1,02:00:00:00:00:01\r\n
 AT+LINK=S1,1,10001,0.0.0.0,0,U1\r\n
 AT+LINK=S2,1,10003,0.0.0.0,0,U1\r\n
 AT+LINK=C1,1,20001,192.168.1.201,10002,U0\r\n
@@ -396,7 +384,6 @@ AT+RESET\r\n
 
 ## 13. 相关文件
 
-- AT 命令实现：`App/config.c`
+- AT 命令实现：[config.c](/D:/code/STM32Project/TCP2UART/App/config.c)
-- 配置结构与默认值：`App/config.h`
+- 配置结构与默认值：[config.h](/D:/code/STM32Project/TCP2UART/App/config.h)
-- FreeRTOS 任务定义：`Core/Src/freertos.c`
+- 调试与测试记录：[uart-ch390-debug-handoff.md](/D:/code/STM32Project/TCP2UART/uart-ch390-debug-handoff.md)
-- 调试指导：`工程调试指南.md`

App/app_runtime.h

@@ -1,44 +0,0 @@
-#ifndef APP_RUNTIME_H
-#define APP_RUNTIME_H
-
-#include <stdint.h>
-#include "FreeRTOS.h"
-#include "queue.h"
-#include "semphr.h"
-#include "task.h"
-#include "config.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern QueueHandle_t xTcpRxQueue;
-extern QueueHandle_t xConfigQueue;
-extern QueueHandle_t xLinkTxQueues[CONFIG_LINK_COUNT];
-extern SemaphoreHandle_t xNetSemaphore;
-
-extern TaskHandle_t xUartRxTaskHandle;
-extern TaskHandle_t xConfigTaskHandle;
-extern volatile BaseType_t g_netif_ready;
-extern volatile uint32_t g_netif_phase;
-extern volatile int32_t g_netif_add_err;
-extern volatile int32_t g_netif_set_default_err;
-extern volatile int32_t g_netif_set_link_down_err;
-extern volatile int32_t g_netif_set_up_err;
-extern volatile int32_t g_netif_init_ok;
-
-void app_start_network_tasks(void);
-void app_request_network_task_stop(void);
-void app_clear_network_task_stop(void);
-BaseType_t app_network_task_stop_requested(void);
-BaseType_t app_network_tasks_are_stopped(void);
-void app_on_network_task_exit(TaskHandle_t task_handle);
-void app_request_network_restart(void);
-void app_clear_network_restart_request(void);
-BaseType_t app_network_restart_requested(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

App/config.c

@@ -1,33 +1,61 @@
+/**
+ * @file config.c
+ * @brief Bare-metal final AT configuration module implementation.
+ */
+
 #include "config.h"
 
+#include "flash_param.h"
+#include "../Core/Inc/usart.h"
+
 #include <stddef.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-#include "flash_param.h"
-#include "usart.h"
-#include "route_msg.h"
-#include "app_runtime.h"
-#include "debug_log.h"
-#include "ethernetif.h"
-#include "uart_trans.h"
-
-#define CONFIG_RX_BUFFER_SIZE   160u
 #define CONFIG_TX_BUFFER_SIZE   512u
 #define CONFIG_CMD_MAX_LEN      160u
 
+#define CONFIG_UART_HANDLE      huart1
+
+typedef struct {
+    uint32_t magic;
+    uint16_t version;
+    uint16_t reserved;
+    uint8_t mac[6];
+    uint8_t dhcp_enable;
+    uint8_t reserved2;
+    uint8_t ip[4];
+    uint8_t mask[4];
+    uint8_t gw[4];
+    uint16_t server_port;
+    uint16_t reserved3;
+    uint8_t remote_ip[4];
+    uint16_t remote_port;
+    uint16_t reconnect_interval;
+    uint32_t uart2_baudrate;
+    uint32_t uart3_baudrate;
+    uint8_t uart2_databits;
+    uint8_t uart2_stopbits;
+    uint8_t uart2_parity;
+    uint8_t uart3_databits;
+    uint8_t uart3_stopbits;
+    uint8_t uart3_parity;
+    uint16_t reserved4;
+    uint32_t crc;
+} legacy_device_config_v2_t;
+
 static device_config_t g_config;
 static volatile bool g_reset_requested;
-static volatile bool g_uart1_tx_busy;
+static uint8_t g_uart_cmd_buffer[CONFIG_CMD_MAX_LEN];
-static volatile uint32_t g_config_rx_route_fail_count;
+static uint16_t g_uart_cmd_len;
-static volatile route_send_result_t g_config_rx_route_fail_reason;
+static bool g_uart_rx_seen_cr;
-static uint8_t g_uart1_rx_buffer[CONFIG_RX_BUFFER_SIZE];
+static char g_pending_cmd_buffer[CONFIG_CMD_MAX_LEN];
-static char g_config_cmd_buffer[CONFIG_CMD_MAX_LEN];
+static volatile uint16_t g_pending_cmd_len;
-static char g_config_response_buffer[CONFIG_TX_BUFFER_SIZE];
+static volatile bool g_pending_cmd_ready;
+static char g_at_response_buffer[CONFIG_TX_BUFFER_SIZE];
+static char g_cmd_parse_buffer[CONFIG_CMD_MAX_LEN];
+static char g_cmd_work_buffer[CONFIG_CMD_MAX_LEN];
 
 static uint32_t config_calc_crc(const device_config_t *cfg)
 {
@@ -45,6 +73,7 @@ static const char *skip_whitespace(const char *str)
 static void trim_trailing(char *str)
 {
     int len = (int)strlen(str);
+
     while (len > 0 && (str[len - 1] == ' ' || str[len - 1] == '\t' || str[len - 1] == '\r' || str[len - 1] == '\n')) {
         str[--len] = '\0';
     }
@@ -55,12 +84,14 @@ static bool equals_ignore_case(const char *a, const char *b)
     while (*a != '\0' && *b != '\0') {
         char c1 = *a++;
         char c2 = *b++;
+
         if (c1 >= 'a' && c1 <= 'z') {
             c1 -= 32;
         }
         if (c2 >= 'a' && c2 <= 'z') {
             c2 -= 32;
         }
+
         if (c1 != c2) {
             return false;
         }
@@ -74,6 +105,7 @@ static int prefix_equals_ignore_case(const char *str, const char *prefix)
     while (*prefix != '\0') {
         char c1 = *str++;
         char c2 = *prefix++;
+
         if (c1 >= 'a' && c1 <= 'z') {
             c1 -= 32;
         }
@@ -92,6 +124,10 @@ static int parse_u32_value(const char *value, uint32_t min_value, uint32_t max_v
     char *endptr;
     unsigned long parsed;
 
+    if (value == NULL || parsed_value == NULL) {
+        return -1;
+    }
+
     parsed = strtoul(value, &endptr, 10);
     if (endptr == value || *skip_whitespace(endptr) != '\0') {
         return -1;
@@ -99,6 +135,7 @@ static int parse_u32_value(const char *value, uint32_t min_value, uint32_t max_v
     if (parsed < min_value || parsed > max_value) {
         return -1;
     }
+
     *parsed_value = (uint32_t)parsed;
     return 0;
 }
@@ -116,19 +153,6 @@ static int parse_link_uart(const char *value, uint8_t *uart)
     return -1;
 }
 
-static int parse_uart_name(const char *value, uint8_t *uart_index)
-{
-    if (equals_ignore_case(value, "U0") || equals_ignore_case(value, "UART2")) {
-        *uart_index = LINK_UART_U0;
-        return 0;
-    }
-    if (equals_ignore_case(value, "U1") || equals_ignore_case(value, "UART3")) {
-        *uart_index = LINK_UART_U1;
-        return 0;
-    }
-    return -1;
-}
-
 static const char *link_uart_to_str(uint8_t uart)
 {
     return (uart == LINK_UART_U1) ? "U1" : "U0";
@@ -150,17 +174,12 @@ static const char *link_index_to_name(uint32_t index)
     }
 }
 
-static void config_get_display_mac(uint8_t *mac)
-{
-    if (ethernetif_get_effective_mac(mac) != 0u) {
-        return;
-    }
-
-    memcpy(mac, g_config.net.mac, sizeof(g_config.net.mac));
-}
-
 static int parse_link_name(const char *value, uint32_t *index)
 {
+    if (value == NULL || index == NULL) {
+        return -1;
+    }
+
     if (equals_ignore_case(value, "S1")) {
         *index = CONFIG_LINK_S1;
         return 0;
@@ -177,24 +196,40 @@ static int parse_link_name(const char *value, uint32_t *index)
         *index = CONFIG_LINK_C2;
         return 0;
     }
+
     return -1;
 }
 
 static bool parse_command_with_value(const char *cmd, const char *name, const char **value)
 {
-    size_t name_len = strlen(name);
+    size_t name_len;
-    if (!prefix_equals_ignore_case(cmd, name) || cmd[name_len] != '=') {
+
+    if (cmd == NULL || name == NULL || value == NULL) {
         return false;
     }
+
+    name_len = strlen(name);
+    if (!prefix_equals_ignore_case(cmd, name)) {
+        return false;
+    }
+    if (cmd[name_len] != '=') {
+        return false;
+    }
+
     *value = skip_whitespace(cmd + name_len + 1u);
     return true;
 }
 
 static char *config_next_token(char **cursor)
 {
-    char *start = *cursor;
+    char *start;
     char *end;
 
+    if (cursor == NULL || *cursor == NULL) {
+        return NULL;
+    }
+
+    start = *cursor;
     while (*start == ' ' || *start == '\t') {
         ++start;
     }
@@ -214,6 +249,7 @@ static char *config_next_token(char **cursor)
     } else {
         *cursor = NULL;
     }
+
     trim_trailing(start);
     return start;
 }
@@ -225,6 +261,7 @@ static void set_link_defaults(void)
     static const uint8_t c2_ip[4] = {192u, 168u, 1u, 201u};
 
     memset(g_config.links, 0, sizeof(g_config.links));
+
     g_config.links[CONFIG_LINK_S1].enabled = 1u;
     g_config.links[CONFIG_LINK_S1].uart = LINK_UART_U0;
     g_config.links[CONFIG_LINK_S1].local_port = 8080u;
@@ -248,22 +285,67 @@ static void set_link_defaults(void)
     g_config.links[CONFIG_LINK_C2].remote_port = 9001u;
 }
 
+static void migrate_legacy_config(const legacy_device_config_v2_t *legacy)
+{
+    config_set_defaults();
+
+    memcpy(g_config.net.mac, legacy->mac, sizeof(g_config.net.mac));
+    memcpy(g_config.net.ip, legacy->ip, sizeof(g_config.net.ip));
+    memcpy(g_config.net.mask, legacy->mask, sizeof(g_config.net.mask));
+    memcpy(g_config.net.gw, legacy->gw, sizeof(g_config.net.gw));
+    g_config.uart_baudrate[0] = legacy->uart2_baudrate;
+    g_config.uart_baudrate[1] = legacy->uart3_baudrate;
+    g_config.mux_mode = MUX_MODE_RAW;
+
+    g_config.links[CONFIG_LINK_S1].enabled = (legacy->server_port != 0u) ? 1u : 0u;
+    g_config.links[CONFIG_LINK_S1].uart = LINK_UART_U0;
+    g_config.links[CONFIG_LINK_S1].local_port = legacy->server_port;
+    memset(g_config.links[CONFIG_LINK_S1].remote_ip, 0, sizeof(g_config.links[CONFIG_LINK_S1].remote_ip));
+    g_config.links[CONFIG_LINK_S1].remote_port = 0u;
+
+    g_config.links[CONFIG_LINK_S2].enabled = 0u;
+
+    g_config.links[CONFIG_LINK_C1].enabled = (legacy->remote_port != 0u) ? 1u : 0u;
+    g_config.links[CONFIG_LINK_C1].uart = LINK_UART_U1;
+    g_config.links[CONFIG_LINK_C1].local_port = 8081u;
+    memcpy(g_config.links[CONFIG_LINK_C1].remote_ip, legacy->remote_ip, sizeof(g_config.links[CONFIG_LINK_C1].remote_ip));
+    g_config.links[CONFIG_LINK_C1].remote_port = legacy->remote_port;
+
+    g_config.links[CONFIG_LINK_C2].enabled = 0u;
+    g_config.crc = config_calc_crc(&g_config);
+}
+
+static bool try_load_legacy_config(void)
+{
+    legacy_device_config_v2_t legacy;
+    uint32_t expected_crc;
+
+    if (flash_param_read(&legacy, sizeof(legacy)) != 0) {
+        return false;
+    }
+
+    expected_crc = flash_param_crc32(&legacy, offsetof(legacy_device_config_v2_t, crc));
+    if (legacy.magic != CONFIG_MAGIC || legacy.version != 0x0002u || legacy.crc != expected_crc) {
+        return false;
+    }
+
+    migrate_legacy_config(&legacy);
+    return true;
+}
+
 static at_result_t handle_summary_query(char *response, uint16_t max_len)
 {
     char ip_str[16];
     char mask_str[16];
     char gw_str[16];
     char mac_str[18];
-    uint8_t display_mac[6];
     char rip_str[CONFIG_LINK_COUNT][16];
-    uint32_t i;
 
     config_ip_to_str(g_config.net.ip, ip_str);
     config_ip_to_str(g_config.net.mask, mask_str);
     config_ip_to_str(g_config.net.gw, gw_str);
-    config_get_display_mac(display_mac);
+    config_mac_to_str(g_config.net.mac, mac_str);
-    config_mac_to_str(display_mac, mac_str);
+    for (uint32_t i = 0; i < CONFIG_LINK_COUNT; ++i) {
-    for (i = 0; i < CONFIG_LINK_COUNT; ++i) {
         config_ip_to_str(g_config.links[i].remote_ip, rip_str[i]);
     }
 
@@ -283,8 +365,68 @@ static at_result_t handle_summary_query(char *response, uint16_t max_len)
              g_config.links[2].enabled, g_config.links[2].local_port, rip_str[2], g_config.links[2].remote_port, link_uart_to_str(g_config.links[2].uart),
              g_config.links[3].enabled, g_config.links[3].local_port, rip_str[3], g_config.links[3].remote_port, link_uart_to_str(g_config.links[3].uart),
              g_config.mux_mode,
-             (unsigned long)g_config.uart_baudrate[0],
+             g_config.uart_baudrate[0],
-             (unsigned long)g_config.uart_baudrate[1]);
+             g_config.uart_baudrate[1]);
+
+    return AT_OK;
+}
+
+static at_result_t handle_net_query(char *response, uint16_t max_len)
+{
+    char ip_str[16];
+    char mask_str[16];
+    char gw_str[16];
+    char mac_str[18];
+
+    config_ip_to_str(g_config.net.ip, ip_str);
+    config_ip_to_str(g_config.net.mask, mask_str);
+    config_ip_to_str(g_config.net.gw, gw_str);
+    config_mac_to_str(g_config.net.mac, mac_str);
+    snprintf(response, max_len, "+NET:IP=%s,MASK=%s,GW=%s,MAC=%s\r\nOK\r\n", ip_str, mask_str, gw_str, mac_str);
+    return AT_OK;
+}
+
+static at_result_t handle_link_query(uint32_t index, char *response, uint16_t max_len)
+{
+    char rip_str[16];
+
+    if (index >= CONFIG_LINK_COUNT) {
+        snprintf(response, max_len, "ERROR: Invalid route field\r\n");
+        return AT_INVALID_PARAM;
+    }
+
+    config_ip_to_str(g_config.links[index].remote_ip, rip_str);
+    snprintf(response,
+             max_len,
+             "+LINK:%s,EN=%u,LPORT=%u,RIP=%s,RPORT=%u,UART=%s\r\nOK\r\n",
+             link_index_to_name(index),
+             g_config.links[index].enabled,
+             g_config.links[index].local_port,
+             rip_str,
+             g_config.links[index].remote_port,
+             link_uart_to_str(g_config.links[index].uart));
+    return AT_OK;
+}
+
+static at_result_t handle_all_link_query(char *response, uint16_t max_len)
+{
+    char rip_str[CONFIG_LINK_COUNT][16];
+
+    for (uint32_t i = 0; i < CONFIG_LINK_COUNT; ++i) {
+        config_ip_to_str(g_config.links[i].remote_ip, rip_str[i]);
+    }
+
+    snprintf(response,
+             max_len,
+             "+LINK:S1,EN=%u,LPORT=%u,RIP=%s,RPORT=%u,UART=%s\r\n"
+             "+LINK:S2,EN=%u,LPORT=%u,RIP=%s,RPORT=%u,UART=%s\r\n"
+             "+LINK:C1,EN=%u,LPORT=%u,RIP=%s,RPORT=%u,UART=%s\r\n"
+             "+LINK:C2,EN=%u,LPORT=%u,RIP=%s,RPORT=%u,UART=%s\r\n"
+             "OK\r\n",
+             g_config.links[0].enabled, g_config.links[0].local_port, rip_str[0], g_config.links[0].remote_port, link_uart_to_str(g_config.links[0].uart),
+             g_config.links[1].enabled, g_config.links[1].local_port, rip_str[1], g_config.links[1].remote_port, link_uart_to_str(g_config.links[1].uart),
+             g_config.links[2].enabled, g_config.links[2].local_port, rip_str[2], g_config.links[2].remote_port, link_uart_to_str(g_config.links[2].uart),
+             g_config.links[3].enabled, g_config.links[3].local_port, rip_str[3], g_config.links[3].remote_port, link_uart_to_str(g_config.links[3].uart));
     return AT_OK;
 }
 
@@ -303,6 +445,10 @@ int config_load(void)
         return 0;
     }
 
+    if (try_load_legacy_config()) {
+        return 0;
+    }
+
     config_set_defaults();
     return -1;
 }
@@ -333,7 +479,6 @@ void config_set_defaults(void)
     set_link_defaults();
     g_config.uart_baudrate[0] = DEFAULT_UART_BAUDRATE;
     g_config.uart_baudrate[1] = DEFAULT_UART_BAUDRATE;
-    g_config.reconnect_interval_ms = 3000u;
     g_config.crc = config_calc_crc(&g_config);
 }
 
@@ -342,14 +487,6 @@ const device_config_t *config_get(void)
     return &g_config;
 }
 
-uint32_t config_get_uart_baudrate(uint8_t uart_index)
-{
-    if (uart_index >= CONFIG_UART_COUNT) {
-        return DEFAULT_UART_BAUDRATE;
-    }
-    return g_config.uart_baudrate[uart_index];
-}
-
 device_config_t *config_get_mutable(void)
 {
     return &g_config;
@@ -357,14 +494,17 @@ device_config_t *config_get_mutable(void)
 
 at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_len)
 {
-    char cmd_copy[CONFIG_CMD_MAX_LEN];
     const char *value;
     const char *p;
 
-    strncpy(cmd_copy, cmd, sizeof(cmd_copy) - 1u);
+    if (cmd == NULL || response == NULL || max_len == 0u) {
-    cmd_copy[sizeof(cmd_copy) - 1u] = '\0';
+        return AT_ERROR;
-    trim_trailing(cmd_copy);
+    }
-    p = skip_whitespace(cmd_copy);
+
+    strncpy(g_cmd_work_buffer, cmd, sizeof(g_cmd_work_buffer) - 1u);
+    g_cmd_work_buffer[sizeof(g_cmd_work_buffer) - 1u] = '\0';
+    trim_trailing(g_cmd_work_buffer);
+    p = skip_whitespace(g_cmd_work_buffer);
 
     if ((p[0] != 'A' && p[0] != 'a') || (p[1] != 'T' && p[1] != 't')) {
         snprintf(response, max_len, "ERROR: Unknown command\r\n");
@@ -380,7 +520,8 @@ at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_
     }
 
     p += 3;
-    if (equals_ignore_case(p, "?") || equals_ignore_case(p, "QUERY")) {
+
+    if ((equals_ignore_case(p, "?") || equals_ignore_case(p, "QUERY"))) {
         return handle_summary_query(response, max_len);
     }
     if (equals_ignore_case(p, "SAVE")) {
@@ -405,39 +546,6 @@ at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_
         snprintf(response, max_len, "+MUX:%u\r\nOK\r\n", g_config.mux_mode);
         return AT_OK;
     }
-    if (equals_ignore_case(p, "BAUD?")) {
-        snprintf(response, max_len,
-                 "+BAUD:U0=%lu,U1=%lu\r\nOK\r\n",
-                 (unsigned long)g_config.uart_baudrate[0],
-                 (unsigned long)g_config.uart_baudrate[1]);
-        return AT_OK;
-    }
-    if (parse_command_with_value(p, "BAUD", &value)) {
-        char value_copy[48];
-        char *cursor;
-        char *token;
-        uint8_t uart_index;
-        uint32_t baudrate;
-
-        strncpy(value_copy, value, sizeof(value_copy) - 1u);
-        value_copy[sizeof(value_copy) - 1u] = '\0';
-        cursor = value_copy;
-        token = config_next_token(&cursor);
-        if (token == NULL || parse_uart_name(token, &uart_index) != 0) {
-            snprintf(response, max_len, "ERROR: Invalid UART\r\n");
-            return AT_INVALID_PARAM;
-        }
-
-        token = config_next_token(&cursor);
-        if (token == NULL || parse_u32_value(token, 1200u, 921600u, &baudrate) != 0) {
-            snprintf(response, max_len, "ERROR: Invalid baudrate\r\n");
-            return AT_INVALID_PARAM;
-        }
-
-        g_config.uart_baudrate[uart_index] = baudrate;
-        snprintf(response, max_len, "OK\r\n");
-        return AT_NEED_REBOOT;
-    }
     if (parse_command_with_value(p, "MUX", &value)) {
         uint32_t mux_value;
         if (parse_u32_value(value, 0u, 1u, &mux_value) != 0) {
@@ -449,24 +557,12 @@ at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_
         return AT_NEED_REBOOT;
     }
     if (equals_ignore_case(p, "NET?")) {
-        char ip_str[16];
+        return handle_net_query(response, max_len);
-        char mask_str[16];
-        char gw_str[16];
-        char mac_str[18];
-        uint8_t display_mac[6];
-
-        config_ip_to_str(g_config.net.ip, ip_str);
-        config_ip_to_str(g_config.net.mask, mask_str);
-        config_ip_to_str(g_config.net.gw, gw_str);
-        config_get_display_mac(display_mac);
-        config_mac_to_str(display_mac, mac_str);
-        snprintf(response, max_len, "+NET:IP=%s,MASK=%s,GW=%s,MAC=%s\r\nOK\r\n", ip_str, mask_str, gw_str, mac_str);
-        return AT_OK;
     }
     if (parse_command_with_value(p, "NET", &value)) {
         char value_copy[96];
-        char *cursor;
         char *token;
+        char *cursor;
         uint8_t ip[4];
         uint8_t mask[4];
         uint8_t gw[4];
@@ -475,6 +571,7 @@ at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_
         strncpy(value_copy, value, sizeof(value_copy) - 1u);
         value_copy[sizeof(value_copy) - 1u] = '\0';
         cursor = value_copy;
+
         token = config_next_token(&cursor);
         if (token == NULL || config_str_to_ip(token, ip) != 0) {
             snprintf(response, max_len, "ERROR: Invalid IP format\r\n");
@@ -495,6 +592,11 @@ at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_
             snprintf(response, max_len, "ERROR: Invalid MAC format\r\n");
             return AT_INVALID_PARAM;
         }
+        if (config_next_token(&cursor) != NULL) {
+            snprintf(response, max_len, "ERROR: Invalid value\r\n");
+            return AT_INVALID_PARAM;
+        }
+
         memcpy(g_config.net.ip, ip, sizeof(ip));
         memcpy(g_config.net.mask, mask, sizeof(mask));
         memcpy(g_config.net.gw, gw, sizeof(gw));
@@ -503,21 +605,7 @@ at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_
         return AT_NEED_REBOOT;
     }
     if (equals_ignore_case(p, "LINK?")) {
-        char rip_str[CONFIG_LINK_COUNT][16];
+        return handle_all_link_query(response, max_len);
-        uint32_t i;
-        for (i = 0; i < CONFIG_LINK_COUNT; ++i) {
-            config_ip_to_str(g_config.links[i].remote_ip, rip_str[i]);
-        }
-        snprintf(response, max_len,
-                 "+LINK:S1,EN=%u,LPORT=%u,RIP=%s,RPORT=%u,UART=%s\r\n"
-                 "+LINK:S2,EN=%u,LPORT=%u,RIP=%s,RPORT=%u,UART=%s\r\n"
-                 "+LINK:C1,EN=%u,LPORT=%u,RIP=%s,RPORT=%u,UART=%s\r\n"
-                 "+LINK:C2,EN=%u,LPORT=%u,RIP=%s,RPORT=%u,UART=%s\r\nOK\r\n",
-                 g_config.links[0].enabled, g_config.links[0].local_port, rip_str[0], g_config.links[0].remote_port, link_uart_to_str(g_config.links[0].uart),
-                 g_config.links[1].enabled, g_config.links[1].local_port, rip_str[1], g_config.links[1].remote_port, link_uart_to_str(g_config.links[1].uart),
-                 g_config.links[2].enabled, g_config.links[2].local_port, rip_str[2], g_config.links[2].remote_port, link_uart_to_str(g_config.links[2].uart),
-                 g_config.links[3].enabled, g_config.links[3].local_port, rip_str[3], g_config.links[3].remote_port, link_uart_to_str(g_config.links[3].uart));
-        return AT_OK;
     }
     if (parse_command_with_value(p, "LINK", &value)) {
         char value_copy[96];
@@ -533,6 +621,7 @@ at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_
         strncpy(value_copy, value, sizeof(value_copy) - 1u);
         value_copy[sizeof(value_copy) - 1u] = '\0';
         cursor = value_copy;
+
         token = config_next_token(&cursor);
         if (token == NULL || parse_link_name(token, &index) != 0) {
             snprintf(response, max_len, "ERROR: Invalid route field\r\n");
@@ -540,17 +629,7 @@ at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_
         }
         token = config_next_token(&cursor);
         if (token == NULL) {
-            char rip_str[16];
+            return handle_link_query(index, response, max_len);
-            config_ip_to_str(g_config.links[index].remote_ip, rip_str);
-            snprintf(response, max_len,
-                     "+LINK:%s,EN=%u,LPORT=%u,RIP=%s,RPORT=%u,UART=%s\r\nOK\r\n",
-                     link_index_to_name(index),
-                     g_config.links[index].enabled,
-                     g_config.links[index].local_port,
-                     rip_str,
-                     g_config.links[index].remote_port,
-                     link_uart_to_str(g_config.links[index].uart));
-            return AT_OK;
         }
         if (parse_u32_value(token, 0u, 1u, &enabled) != 0) {
             snprintf(response, max_len, "ERROR: Invalid value\r\n");
@@ -576,12 +655,20 @@ at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_
             snprintf(response, max_len, "ERROR: Invalid route field\r\n");
             return AT_INVALID_PARAM;
         }
+        if (config_next_token(&cursor) != NULL) {
+            snprintf(response, max_len, "ERROR: Invalid value\r\n");
+            return AT_INVALID_PARAM;
+        }
+
         g_config.links[index].enabled = (uint8_t)enabled;
         g_config.links[index].local_port = (uint16_t)local_port;
         memcpy(g_config.links[index].remote_ip, rip, sizeof(rip));
         g_config.links[index].remote_port = (uint16_t)remote_port;
         g_config.links[index].uart = uart;
-        snprintf(response, max_len, "OK\r\n");
+        if (handle_link_query(index, response, max_len) != AT_OK) {
+            snprintf(response, max_len, "ERROR: Invalid route field\r\n");
+            return AT_INVALID_PARAM;
+        }
         return AT_NEED_REBOOT;
     }
 
@@ -596,13 +683,18 @@ void config_ip_to_str(const uint8_t *ip, char *str)
 
 int config_str_to_ip(const char *str, uint8_t *ip)
 {
-    int a, b, c, d;
+    int a;
+    int b;
+    int c;
+    int d;
+
     if (sscanf(str, "%d.%d.%d.%d", &a, &b, &c, &d) != 4) {
         return -1;
     }
     if (a < 0 || a > 255 || b < 0 || b > 255 || c < 0 || c > 255 || d < 0 || d > 255) {
         return -1;
     }
+
     ip[0] = (uint8_t)a;
     ip[1] = (uint8_t)b;
     ip[2] = (uint8_t)c;
@@ -618,14 +710,13 @@ void config_mac_to_str(const uint8_t *mac, char *str)
 int config_str_to_mac(const char *str, uint8_t *mac)
 {
     int a[6];
-    int i;
 
     if (sscanf(str, "%x:%x:%x:%x:%x:%x", &a[0], &a[1], &a[2], &a[3], &a[4], &a[5]) != 6 &&
         sscanf(str, "%x-%x-%x-%x-%x-%x", &a[0], &a[1], &a[2], &a[3], &a[4], &a[5]) != 6) {
         return -1;
     }
 
-    for (i = 0; i < 6; ++i) {
+    for (int i = 0; i < 6; ++i) {
         if (a[i] < 0 || a[i] > 255) {
             return -1;
         }
@@ -634,147 +725,110 @@ int config_str_to_mac(const char *str, uint8_t *mac)
     return 0;
 }
 
-void config_uart_idle_handler(void)
+void config_poll(void)
 {
-    uint16_t dma_counter = __HAL_DMA_GET_COUNTER(huart1.hdmarx);
+    if (g_pending_cmd_ready) {
-    uint16_t len = CONFIG_RX_BUFFER_SIZE - dma_counter;
+        uint16_t len = g_pending_cmd_len;
-    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+        g_pending_cmd_ready = false;
-    HAL_StatusTypeDef hal_status;
+        g_pending_cmd_len = 0u;
-    route_send_result_t route_result;
+        (void)config_try_process_frame((const uint8_t *)g_pending_cmd_buffer, len);
-
-    if (g_uart1_tx_busy) {
-        return;
-    }
-
-    if (len > 0u && xConfigQueue != NULL) {
-        route_result = route_send_from_isr(xConfigQueue,
-                                           0u,
-                                           0u,
-                                           ROUTE_CONN_UART1,
-                                           g_uart1_rx_buffer,
-                                           len,
-                                           &xHigherPriorityTaskWoken);
-        if (route_result != ROUTE_SEND_OK) {
-            g_config_rx_route_fail_reason = route_result;
-            g_config_rx_route_fail_count += 1u;
     }
 }
 
-    hal_status = HAL_UART_DMAStop(&huart1);
+void config_uart_rx_byte(uint8_t byte)
-    if (hal_status != HAL_OK) {
-        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
-        return;
-    }
-
-    hal_status = HAL_UART_Receive_DMA(&huart1, g_uart1_rx_buffer, CONFIG_RX_BUFFER_SIZE);
-    if (hal_status != HAL_OK) {
-        __HAL_UART_DISABLE_IT(&huart1, UART_IT_IDLE);
-        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
-        return;
-    }
-
-    portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
-}
-
-void config_start_reception(void)
 {
-    debug_log_write("[CFG] rx-start enter\r\n");
+    if (byte == '\r') {
-    __HAL_UART_ENABLE_IT(&huart1, UART_IT_IDLE);
+        g_uart_rx_seen_cr = true;
-    if (HAL_UART_Receive_DMA(&huart1, g_uart1_rx_buffer, CONFIG_RX_BUFFER_SIZE) != HAL_OK) {
-        debug_log_write("[CFG] rx-start fail\r\n");
-        Debug_TrapWithRttHint("cfg-rx-start-fail");
         return;
     }
-    debug_log_write("[CFG] rx-start exit\r\n");
+
+    if (byte == '\n') {
+        if (g_uart_rx_seen_cr && g_uart_cmd_len > 0u) {
+            if (!g_pending_cmd_ready) {
+                memcpy(g_pending_cmd_buffer, g_uart_cmd_buffer, g_uart_cmd_len);
+                g_pending_cmd_buffer[g_uart_cmd_len] = '\0';
+                g_pending_cmd_len = g_uart_cmd_len;
+                g_pending_cmd_ready = true;
+            }
+            g_uart_cmd_len = 0u;
+        }
+        g_uart_rx_seen_cr = false;
+        return;
     }
 
-static void config_respond_to_uart(route_msg_t *msg, const char *response)
+    if (g_uart_rx_seen_cr) {
-{
+        g_uart_cmd_len = 0u;
-    if (msg->conn_type == ROUTE_CONN_UART1) {
+        g_uart_rx_seen_cr = false;
-        g_uart1_tx_busy = true;
-        __HAL_UART_DISABLE_IT(&huart1, UART_IT_IDLE);
-        (void)HAL_UART_Transmit(&huart1, (const uint8_t *)response, (uint16_t)strlen(response), 200u);
-        __HAL_UART_ENABLE_IT(&huart1, UART_IT_IDLE);
-        g_uart1_tx_busy = false;
-    } else if (msg->src_id == ENDPOINT_UART2 || msg->src_id == ENDPOINT_UART3) {
-        uart_channel_t channel = (msg->src_id == ENDPOINT_UART3) ? UART_CHANNEL_U1 : UART_CHANNEL_U0;
-        uint8_t frame[ROUTE_MSG_MAX_PAYLOAD + 6u];
-        uint16_t frame_len = 0u;
-        uart_trans_send_result_t uart_result;
-        if (uart_mux_encode_frame(msg->src_id, 0u, (const uint8_t *)response, (uint16_t)strlen(response), frame, &frame_len, sizeof(frame))) {
-            uart_result = uart_trans_send_buffer(channel, frame, frame_len);
-            if (uart_result != UART_TRANS_SEND_OK) {
-                debug_log_printf("[CFG] resp-tx-fail ch=%u rc=%s len=%u\r\n",
-                                 (unsigned int)channel,
-                                 uart_trans_send_result_to_str(uart_result),
-                                 (unsigned int)frame_len);
     }
+
+    if (g_uart_cmd_len < (CONFIG_CMD_MAX_LEN - 1u)) {
+        g_uart_cmd_buffer[g_uart_cmd_len++] = byte;
+        g_uart_cmd_buffer[g_uart_cmd_len] = '\0';
     } else {
-            debug_log_printf("[CFG] resp-enc-fail src=0x%02X len=%u\r\n",
+        g_uart_cmd_len = 0u;
-                             (unsigned int)msg->src_id,
-                             (unsigned int)strlen(response));
-        }
     }
 }
 
-static void config_report_route_failures(uint32_t *reported_route_fail_count)
+bool config_build_response_frame(const uint8_t *data,
+                                 uint16_t len,
+                                 char *response,
+                                 uint16_t max_len,
+                                 at_result_t *result)
 {
-    uint32_t fail_count;
+    if (data == NULL || response == NULL || len < 2u || max_len == 0u) {
-    route_send_result_t fail_reason;
+        return false;
-
+    }
-    if (reported_route_fail_count == NULL) {
+    if (len >= CONFIG_CMD_MAX_LEN) {
-        return;
+        return false;
     }
 
-    fail_count = g_config_rx_route_fail_count;
+    memcpy(g_cmd_parse_buffer, data, len);
-    fail_reason = g_config_rx_route_fail_reason;
+    g_cmd_parse_buffer[len] = '\0';
-    if (fail_count != *reported_route_fail_count) {
+    if (((g_cmd_parse_buffer[0] != 'A') && (g_cmd_parse_buffer[0] != 'a')) ||
-        *reported_route_fail_count = fail_count;
+        ((g_cmd_parse_buffer[1] != 'T') && (g_cmd_parse_buffer[1] != 't'))) {
-        debug_log_printf("[CFG] rx-route-fail rc=%s cnt=%lu\r\n",
+        return false;
-                         route_send_result_to_str(fail_reason),
-                         (unsigned long)fail_count);
-    }
     }
 
-void ConfigTask(void *argument)
+    *result = config_process_at_cmd(g_cmd_parse_buffer, response, max_len);
+    return true;
+}
+
+bool config_try_process_frame(const uint8_t *data, uint16_t len)
 {
-    route_msg_t *msg;
+    at_result_t result = AT_ERROR;
-    at_result_t result;
-    uint32_t reported_route_fail_count = 0u;
 
-    (void)argument;
+    if (!config_build_response_frame(data, len, g_at_response_buffer, sizeof(g_at_response_buffer), &result)) {
-    debug_log_write("[CFG] task-entry\r\n");
+        return false;
-    config_start_reception();
-    debug_log_write("[CFG] task-ready\r\n");
-
-    for (;;) {
-        config_report_route_failures(&reported_route_fail_count);
-
-        if (xQueueReceive(xConfigQueue, &msg, pdMS_TO_TICKS(50)) != pdPASS) {
-            continue;
     }
 
-        config_report_route_failures(&reported_route_fail_count);
+    if (HAL_UART_Transmit(&CONFIG_UART_HANDLE,
-
+                          (uint8_t *)g_at_response_buffer,
-        if (msg->len >= sizeof(g_config_cmd_buffer)) {
+                          (uint16_t)strlen(g_at_response_buffer),
-            msg->len = sizeof(g_config_cmd_buffer) - 1u;
+                          1000u) != HAL_OK) {
+        return false;
     }
-        memcpy(g_config_cmd_buffer, msg->data, msg->len);
-        g_config_cmd_buffer[msg->len] = '\0';
 
-        result = config_process_at_cmd(g_config_cmd_buffer, g_config_response_buffer, sizeof(g_config_response_buffer));
-        config_respond_to_uart(msg, g_config_response_buffer);
     if (result == AT_NEED_REBOOT) {
-            config_respond_to_uart(msg, "Note: Use AT+SAVE then AT+RESET to apply changes\r\n");
+        static const char hint[] = "Note: Use AT+SAVE then AT+RESET to apply changes\r\n";
+        if (HAL_UART_Transmit(&CONFIG_UART_HANDLE,
+                              (uint8_t *)hint,
+                              sizeof(hint) - 1u,
+                              1000u) != HAL_OK) {
+            return false;
+        }
     }
-        route_msg_free(msg);
 
-        if (g_reset_requested) {
+    return true;
+}
+
+bool config_is_reset_requested(void)
+{
+    return g_reset_requested;
+}
+
+void config_clear_reset_requested(void)
+{
     g_reset_requested = false;
-            vTaskDelay(pdMS_TO_TICKS(100));
-            NVIC_SystemReset();
-        }
-    }
 }
 
 uint8_t config_link_index_to_endpoint(uint8_t index)

App/config.h

@@ -1,5 +1,10 @@
-#ifndef CONFIG_H
+/**
-#define CONFIG_H
+ * @file config.h
+ * @brief Final AT configuration model for TCP2UART.
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
 
 #include <stdbool.h>
 #include <stdint.h>
@@ -59,18 +64,15 @@ typedef struct {
     net_config_t net;
     link_config_t links[CONFIG_LINK_COUNT];
     uint32_t uart_baudrate[CONFIG_UART_COUNT];
-    uint32_t reconnect_interval_ms;
     uint32_t crc;
 } device_config_t;
 
-#define DEFAULT_NET_IP           {192, 168, 31, 100}
+#define DEFAULT_NET_IP           {192, 168, 1, 100}
 #define DEFAULT_NET_MASK         {255, 255, 255, 0}
-#define DEFAULT_NET_GW           {192, 168, 31, 1}
+#define DEFAULT_NET_GW           {192, 168, 1, 1}
-#define DEFAULT_NET_MAC          {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+#define DEFAULT_NET_MAC          {0x02, 0x00, 0x00, 0x00, 0x00, 0x01}
 #define DEFAULT_UART_BAUDRATE    115200u
 
-#define DIAG_CH390_RAW_POLL      0
-
 typedef enum {
     AT_OK = 0,
     AT_ERROR,
@@ -86,11 +88,17 @@ int config_save(void);
 void config_set_defaults(void);
 const device_config_t *config_get(void);
 device_config_t *config_get_mutable(void);
-uint32_t config_get_uart_baudrate(uint8_t uart_index);
 at_result_t config_process_at_cmd(const char *cmd, char *response, uint16_t max_len);
-void ConfigTask(void *argument);
+void config_poll(void);
-void config_uart_idle_handler(void);
+void config_uart_rx_byte(uint8_t byte);
-void config_start_reception(void);
+bool config_try_process_frame(const uint8_t *data, uint16_t len);
+bool config_build_response_frame(const uint8_t *data,
+                                 uint16_t len,
+                                 char *response,
+                                 uint16_t max_len,
+                                 at_result_t *result);
+bool config_is_reset_requested(void);
+void config_clear_reset_requested(void);
 void config_ip_to_str(const uint8_t *ip, char *str);
 int config_str_to_ip(const char *str, uint8_t *ip);
 void config_mac_to_str(const uint8_t *mac, char *str);
@@ -103,4 +111,4 @@ bool config_endpoint_is_single(uint8_t endpoint);
 }
 #endif
 
-#endif
+#endif /* __CONFIG_H__ */

App/flash_param.c

@@ -19,41 +19,10 @@
  * Private Variables
  *---------------------------------------------------------------------------*/
 
-/* CRC32 lookup table */
-static uint32_t g_crc_table[256];
-static bool g_crc_table_initialized = false;
-
 /*---------------------------------------------------------------------------
  * Private Functions
  *---------------------------------------------------------------------------*/
 
-/**
- * @brief Initialize CRC32 lookup table
- */
-static void crc32_init_table(void)
-{
-    uint32_t i, j, crc;
-    
-    for (i = 0; i < 256; i++)
-    {
-        crc = i;
-        for (j = 0; j < 8; j++)
-        {
-            if (crc & 1)
-            {
-                crc = (crc >> 1) ^ CRC32_POLYNOMIAL;
-            }
-            else
-            {
-                crc >>= 1;
-            }
-        }
-        g_crc_table[i] = crc;
-    }
-    
-    g_crc_table_initialized = true;
-}
-
 /**
  * @brief Unlock Flash for writing
  */
@@ -105,12 +74,6 @@ static HAL_StatusTypeDef flash_program_halfword(uint32_t addr, uint16_t data)
  */
 int flash_param_init(void)
 {
-    /* Initialize CRC table */
-    if (!g_crc_table_initialized)
-    {
-        crc32_init_table();
-    }
-    
     return 0;
 }
 
@@ -243,16 +206,22 @@ uint32_t flash_param_crc32(const void *data, uint32_t len)
     const uint8_t *p = (const uint8_t *)data;
     uint32_t crc = 0xFFFFFFFF;
     uint32_t i;
-    
+    uint32_t j;
-    /* Initialize table if needed */
-    if (!g_crc_table_initialized)
-    {
-        crc32_init_table();
-    }
 
     for (i = 0; i < len; i++)
     {
-        crc = g_crc_table[(crc ^ p[i]) & 0xFF] ^ (crc >> 8);
+        crc ^= p[i];
+        for (j = 0; j < 8u; ++j)
+        {
+            if ((crc & 1u) != 0u)
+            {
+                crc = (crc >> 1) ^ CRC32_POLYNOMIAL;
+            }
+            else
+            {
+                crc >>= 1;
+            }
+        }
     }
     
     return crc ^ 0xFFFFFFFF;

App/flash_param.h

@@ -16,12 +16,13 @@
 extern "C" {
 #endif
 
-/* Flash configuration for the current STM32F103RDT6 target (384KB Flash). */
+/* Flash configuration for STM32F103R8 (64KB Flash) */
 #define FLASH_PARAM_PAGE_SIZE       1024        /* 1KB per page for STM32F103 */
-#define FLASH_PARAM_START_ADDR      0x0805FC00  /* Last 1KB page of 384KB Flash */
+#define FLASH_PARAM_START_ADDR      0x0800FC00  /* Last 1KB of 64KB Flash */
-#define FLASH_PARAM_END_ADDR        0x08060000  /* End of 384KB Flash */
+#define FLASH_PARAM_END_ADDR        0x08010000  /* End of Flash */
 
-/* Historical reference: STM32F103RCT6 would use 0x0803FC00 as its last page. */
+/* For STM32F103RC (256KB), use: 0x0803FC00 */
+/* For STM32F103RB (128KB), use: 0x0801FC00 */
 
 /**
  * @brief Initialize Flash parameter storage

App/route_msg.c

@@ -1,227 +0,0 @@
-#include "route_msg.h"
-
-#include <string.h>
-
-#include "task.h"
-
-typedef struct {
-    route_msg_t msg;
-    uint8_t data[ROUTE_MSG_MAX_PAYLOAD];
-    uint8_t in_use;
-} route_slot_t;
-
-static route_slot_t g_route_slots[ROUTE_MSG_POOL_SIZE];
-
-const char *route_send_result_to_str(route_send_result_t result)
-{
-    switch (result) {
-    case ROUTE_SEND_OK:
-        return "ok";
-    case ROUTE_SEND_INVALID_INPUT:
-        return "invalid";
-    case ROUTE_SEND_POOL_EXHAUSTED:
-        return "pool";
-    case ROUTE_SEND_QUEUE_FULL:
-        return "queue";
-    default:
-        return "unknown";
-    }
-}
-
-void route_msg_init(void)
-{
-    memset(g_route_slots, 0, sizeof(g_route_slots));
-}
-
-static route_msg_t *route_msg_try_alloc_locked(void)
-{
-    uint32_t index;
-
-    for (index = 0; index < ROUTE_MSG_POOL_SIZE; ++index) {
-        if (g_route_slots[index].in_use == 0u) {
-            g_route_slots[index].in_use = 1u;
-            g_route_slots[index].msg.data = g_route_slots[index].data;
-            g_route_slots[index].msg.len = 0u;
-            g_route_slots[index].msg.src_id = 0u;
-            g_route_slots[index].msg.dst_mask = 0u;
-            g_route_slots[index].msg.conn_type = 0u;
-            return &g_route_slots[index].msg;
-        }
-    }
-
-    return NULL;
-}
-
-route_msg_t *route_msg_alloc(TickType_t wait_ticks)
-{
-    TickType_t start_tick = xTaskGetTickCount();
-    route_msg_t *msg;
-
-    do {
-        taskENTER_CRITICAL();
-        msg = route_msg_try_alloc_locked();
-        taskEXIT_CRITICAL();
-        if (msg != NULL) {
-            return msg;
-        }
-        if (wait_ticks == 0u) {
-            break;
-        }
-        vTaskDelay(pdMS_TO_TICKS(1));
-    } while ((xTaskGetTickCount() - start_tick) < wait_ticks);
-
-    return NULL;
-}
-
-route_msg_t *route_msg_alloc_from_isr(BaseType_t *xHigherPriorityTaskWoken)
-{
-    route_msg_t *msg;
-    UBaseType_t saved_interrupt_status;
-
-    (void)xHigherPriorityTaskWoken;
-    saved_interrupt_status = taskENTER_CRITICAL_FROM_ISR();
-    msg = route_msg_try_alloc_locked();
-    taskEXIT_CRITICAL_FROM_ISR(saved_interrupt_status);
-    return msg;
-}
-
-void route_msg_free(route_msg_t *msg)
-{
-    uint32_t index;
-
-    if (msg == NULL) {
-        return;
-    }
-
-    taskENTER_CRITICAL();
-    for (index = 0; index < ROUTE_MSG_POOL_SIZE; ++index) {
-        if (&g_route_slots[index].msg == msg) {
-            g_route_slots[index].in_use = 0u;
-            g_route_slots[index].msg.len = 0u;
-            break;
-        }
-    }
-    taskEXIT_CRITICAL();
-}
-
-void route_msg_free_from_isr(route_msg_t *msg)
-{
-    uint32_t index;
-    UBaseType_t saved_interrupt_status;
-
-    if (msg == NULL) {
-        return;
-    }
-
-    saved_interrupt_status = taskENTER_CRITICAL_FROM_ISR();
-    for (index = 0; index < ROUTE_MSG_POOL_SIZE; ++index) {
-        if (&g_route_slots[index].msg == msg) {
-            g_route_slots[index].in_use = 0u;
-            g_route_slots[index].msg.len = 0u;
-            break;
-        }
-    }
-    taskEXIT_CRITICAL_FROM_ISR(saved_interrupt_status);
-}
-
-static route_send_result_t route_prepare(route_msg_t *msg,
-                                         uint8_t src_id,
-                                         uint8_t dst_mask,
-                                         uint8_t conn_type,
-                                         const uint8_t *data,
-                                         uint16_t len)
-{
-    if (msg == NULL || data == NULL || len == 0u || len > ROUTE_MSG_MAX_PAYLOAD) {
-        return ROUTE_SEND_INVALID_INPUT;
-    }
-
-    msg->src_id = src_id;
-    msg->dst_mask = dst_mask;
-    msg->conn_type = conn_type;
-    msg->len = len;
-    memcpy(msg->data, data, len);
-    return ROUTE_SEND_OK;
-}
-
-static route_send_result_t route_validate_args(QueueHandle_t queue,
-                                               const uint8_t *data,
-                                               uint16_t len)
-{
-    if (queue == NULL || data == NULL || len == 0u || len > ROUTE_MSG_MAX_PAYLOAD) {
-        return ROUTE_SEND_INVALID_INPUT;
-    }
-
-    return ROUTE_SEND_OK;
-}
-
-route_send_result_t route_send(QueueHandle_t queue,
-                               uint8_t src_id,
-                               uint8_t dst_mask,
-                               uint8_t conn_type,
-                               const uint8_t *data,
-                               uint16_t len,
-                               TickType_t wait_ticks)
-{
-    route_send_result_t result;
-    route_msg_t *msg;
-
-    result = route_validate_args(queue, data, len);
-    if (result != ROUTE_SEND_OK) {
-        return result;
-    }
-
-    msg = route_msg_alloc(wait_ticks);
-
-    if (msg == NULL) {
-        return ROUTE_SEND_POOL_EXHAUSTED;
-    }
-
-    result = route_prepare(msg, src_id, dst_mask, conn_type, data, len);
-    if (result != ROUTE_SEND_OK) {
-        route_msg_free(msg);
-        return result;
-    }
-
-    if (xQueueSend(queue, &msg, wait_ticks) != pdPASS) {
-        route_msg_free(msg);
-        return ROUTE_SEND_QUEUE_FULL;
-    }
-
-    return ROUTE_SEND_OK;
-}
-
-route_send_result_t route_send_from_isr(QueueHandle_t queue,
-                                        uint8_t src_id,
-                                        uint8_t dst_mask,
-                                        uint8_t conn_type,
-                                        const uint8_t *data,
-                                        uint16_t len,
-                                        BaseType_t *xHigherPriorityTaskWoken)
-{
-    route_send_result_t result;
-    route_msg_t *msg;
-
-    result = route_validate_args(queue, data, len);
-    if (result != ROUTE_SEND_OK) {
-        return result;
-    }
-
-    msg = route_msg_alloc_from_isr(xHigherPriorityTaskWoken);
-
-    if (msg == NULL) {
-        return ROUTE_SEND_POOL_EXHAUSTED;
-    }
-
-    result = route_prepare(msg, src_id, dst_mask, conn_type, data, len);
-    if (result != ROUTE_SEND_OK) {
-        route_msg_free_from_isr(msg);
-        return result;
-    }
-
-    if (xQueueSendFromISR(queue, &msg, xHigherPriorityTaskWoken) != pdPASS) {
-        route_msg_free_from_isr(msg);
-        return ROUTE_SEND_QUEUE_FULL;
-    }
-
-    return ROUTE_SEND_OK;
-}

App/route_msg.h

@@ -1,72 +0,0 @@
-#ifndef ROUTE_MSG_H
-#define ROUTE_MSG_H
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#include "FreeRTOS.h"
-#include "queue.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef ROUTE_MSG_POOL_SIZE
-#define ROUTE_MSG_POOL_SIZE   8u
-#endif
-
-#ifndef ROUTE_MSG_MAX_PAYLOAD
-#define ROUTE_MSG_MAX_PAYLOAD 512u
-#endif
-
-typedef enum {
-    ROUTE_CONN_UART1 = 0,
-    ROUTE_CONN_UART2,
-    ROUTE_CONN_UART3,
-    ROUTE_CONN_S1,
-    ROUTE_CONN_S2,
-    ROUTE_CONN_C1,
-    ROUTE_CONN_C2
-} route_conn_type_t;
-
-typedef enum {
-    ROUTE_SEND_OK = 0,
-    ROUTE_SEND_INVALID_INPUT,
-    ROUTE_SEND_POOL_EXHAUSTED,
-    ROUTE_SEND_QUEUE_FULL
-} route_send_result_t;
-
-typedef struct {
-    uint8_t src_id;
-    uint8_t dst_mask;
-    uint16_t len;
-    uint8_t conn_type;
-    uint8_t *data;
-} route_msg_t;
-
-void route_msg_init(void);
-route_msg_t *route_msg_alloc(TickType_t wait_ticks);
-route_msg_t *route_msg_alloc_from_isr(BaseType_t *xHigherPriorityTaskWoken);
-void route_msg_free(route_msg_t *msg);
-void route_msg_free_from_isr(route_msg_t *msg);
-const char *route_send_result_to_str(route_send_result_t result);
-route_send_result_t route_send(QueueHandle_t queue,
-                               uint8_t src_id,
-                               uint8_t dst_mask,
-                               uint8_t conn_type,
-                               const uint8_t *data,
-                               uint16_t len,
-                               TickType_t wait_ticks);
-route_send_result_t route_send_from_isr(QueueHandle_t queue,
-                                        uint8_t src_id,
-                                        uint8_t dst_mask,
-                                        uint8_t conn_type,
-                                        const uint8_t *data,
-                                        uint16_t len,
-                                        BaseType_t *xHigherPriorityTaskWoken);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

App/task_net_poll.c

@@ -1,192 +0,0 @@
-#include "task_net_poll.h"
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "semphr.h"
-#include "CH390.h"
-#include <string.h>
-
-#if !DIAG_CH390_RAW_POLL
-#include "lwip/tcpip.h"
-#include "lwip/ip4_addr.h"
-#endif
-
-#include "ethernetif.h"
-#include "config.h"
-#include "app_runtime.h"
-#include "debug_log.h"
-
-#define CH390_RESTART_HOLD_DOWN_MS          500u
-#define NETWORK_TASK_DELETE_SETTLE_MS       50u
-#define CH390_EXPECTED_VENDOR_ID            0x1C00u
-#define CH390_EXPECTED_PRODUCT_ID           0x9151u
-
-static void net_poll_wait_for_network_tasks_stop(void)
-{
-    while (app_network_tasks_are_stopped() == pdFALSE) {
-        vTaskDelay(pdMS_TO_TICKS(20));
-    }
-}
-
-static BaseType_t net_poll_restart_network_stack(const device_config_t *cfg)
-{
-#if !DIAG_CH390_RAW_POLL
-    ip4_addr_t ipaddr;
-    ip4_addr_t netmask;
-    ip4_addr_t gateway;
-    uint16_t vendor_id;
-    uint16_t product_id;
-    uint8_t revision;
-
-    IP4_ADDR(&ipaddr, cfg->net.ip[0], cfg->net.ip[1], cfg->net.ip[2], cfg->net.ip[3]);
-    IP4_ADDR(&netmask, cfg->net.mask[0], cfg->net.mask[1], cfg->net.mask[2], cfg->net.mask[3]);
-    IP4_ADDR(&gateway, cfg->net.gw[0], cfg->net.gw[1], cfg->net.gw[2], cfg->net.gw[3]);
-#endif
-
-    ethernetif_force_link_down();
-    g_netif_ready = pdFALSE;
-    app_request_network_task_stop();
-    net_poll_wait_for_network_tasks_stop();
-    vTaskDelay(pdMS_TO_TICKS(NETWORK_TASK_DELETE_SETTLE_MS));
-    vTaskDelay(pdMS_TO_TICKS(CH390_RESTART_HOLD_DOWN_MS));
-
-#if DIAG_CH390_RAW_POLL
-    ethernetif_diag_ch390_init();
-#else
-    ethernetif_force_full_recovery(&ipaddr, &netmask, &gateway, cfg->net.mac);
-    vendor_id = ethernetif_ch390_get_vendor_id();
-    product_id = ethernetif_ch390_get_product_id();
-    revision = ethernetif_ch390_get_revision();
-    if ((vendor_id != CH390_EXPECTED_VENDOR_ID) || (product_id != CH390_EXPECTED_PRODUCT_ID)) {
-        debug_log_printf("[NET] restart-recovery id-warn vid=0x%04X pid=0x%04X rev=0x%02X free=%lu min=%lu\r\n",
-                         (unsigned int)vendor_id,
-                         (unsigned int)product_id,
-                         (unsigned int)revision,
-                         (unsigned long)xPortGetFreeHeapSize(),
-                         (unsigned long)xPortGetMinimumEverFreeHeapSize());
-    }
-#endif
-
-    app_clear_network_task_stop();
-    g_netif_ready = pdTRUE;
-    app_start_network_tasks();
-    app_clear_network_restart_request();
-    return pdTRUE;
-}
-
-void NetPollTask(void *argument)
-{
-    const device_config_t *cfg;
-#if !DIAG_CH390_RAW_POLL
-    ip4_addr_t ipaddr;
-    ip4_addr_t netmask;
-    ip4_addr_t gateway;
-#else
-    static uint8_t s_diag_rx_buffer[CH390_PKT_MAX];
-#endif
-    BaseType_t loop_logged = pdFALSE;
-
-    (void)argument;
-
-    debug_log_write("[NET] task-entry\r\n");
-    cfg = config_get();
-    debug_log_write("[NET] config-ok\r\n");
-
-#if DIAG_CH390_RAW_POLL
-    g_netif_phase = 1u;
-    debug_log_write("[NET] diag-ch390-init enter\r\n");
-    ethernetif_diag_ch390_init();
-    g_netif_phase = 7u;
-    debug_log_write("[NET] diag-ch390-init exit\r\n");
-
-    if (g_netif_init_ok != 1)
-    {
-        for (;;)
-        {
-            vTaskDelay(pdMS_TO_TICKS(1000));
-        }
-    }
-
-    g_netif_ready = pdTRUE;
-    app_start_network_tasks();
-    debug_log_write("[NET] diag-ch390-ready\r\n");
-#else
-    debug_log_write("[NET] tcpip-init enter\r\n");
-    tcpip_init(NULL, NULL);
-    debug_log_write("[NET] tcpip-init exit\r\n");
-
-    vTaskDelay(pdMS_TO_TICKS(50));
-    debug_log_write("[NET] post-delay\r\n");
-
-    IP4_ADDR(&ipaddr, cfg->net.ip[0], cfg->net.ip[1], cfg->net.ip[2], cfg->net.ip[3]);
-    IP4_ADDR(&netmask, cfg->net.mask[0], cfg->net.mask[1], cfg->net.mask[2], cfg->net.mask[3]);
-    IP4_ADDR(&gateway, cfg->net.gw[0], cfg->net.gw[1], cfg->net.gw[2], cfg->net.gw[3]);
-
-    g_netif_phase = 1u;
-    debug_log_printf("[NET] netif-call hwm=%lu\r\n", (unsigned long)uxTaskGetStackHighWaterMark(NULL));
-    debug_log_write("[NET] netif-init enter\r\n");
-    lwip_netif_init(&ipaddr, &netmask, &gateway);
-    g_netif_phase = 7u;
-    debug_log_write("[NET] netif-init exit\r\n");
-    debug_log_printf("[NET] post-init ok=%ld hwm=%lu free=%lu min=%lu\r\n",
-                     (long)g_netif_init_ok,
-                     (unsigned long)uxTaskGetStackHighWaterMark(NULL),
-                     (unsigned long)xPortGetFreeHeapSize(),
-                     (unsigned long)xPortGetMinimumEverFreeHeapSize());
-
-    if (g_netif_init_ok != 1) {
-        for (;;) {
-            vTaskDelay(pdMS_TO_TICKS(1000));
-        }
-    }
-
-    debug_log_write("[NET] pre-ready\r\n");
-    g_netif_ready = pdTRUE;
-    debug_log_write("[NET] start-network-tasks call\r\n");
-    app_start_network_tasks();
-    debug_log_printf("[NET] post-ready free=%lu min=%lu\r\n",
-                     (unsigned long)xPortGetFreeHeapSize(),
-                     (unsigned long)xPortGetMinimumEverFreeHeapSize());
-    debug_log_write("[NET] netif-ready\r\n");
-#endif
-
-    for (;;) {
-        if (loop_logged == pdFALSE) {
-            g_netif_phase = 8u;
-            debug_log_write("[NET] loop-enter\r\n");
-            loop_logged = pdTRUE;
-        }
-
-        if (app_network_restart_requested() != pdFALSE) {
-            (void)net_poll_restart_network_stack(cfg);
-        }
-
-        (void)xSemaphoreTake(xNetSemaphore, pdMS_TO_TICKS(2));
-
-#if DIAG_CH390_RAW_POLL
-        ethernetif_diag_poll_status();
-
-        if (ch390_read_reg(CH390_NSR) & NSR_RXRDY)
-        {
-            uint8_t rx_status = 0u;
-            uint32_t rx_len = ch390_runtime_receive_packet(s_diag_rx_buffer, &rx_status);
-
-            if (rx_len > 0u)
-            {
-                debug_log_printf("[RAW] rx len=%lu st=0x%02X h=%02X %02X %02X %02X\r\n",
-                                 (unsigned long)rx_len,
-                                 (unsigned int)rx_status,
-                                 (unsigned int)s_diag_rx_buffer[0],
-                                 (unsigned int)s_diag_rx_buffer[1],
-                                 (unsigned int)s_diag_rx_buffer[2],
-                                 (unsigned int)s_diag_rx_buffer[3]);
-            }
-        }
-#else
-        if (g_netif_ready != pdFALSE) {
-            ethernetif_poll();
-            ethernetif_check_link();
-        }
-#endif
-    }
-}

App/task_net_poll.h

@@ -1,14 +0,0 @@
-#ifndef TASK_NET_POLL_H
-#define TASK_NET_POLL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NetPollTask(void *argument);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

App/tcp_client.c

@@ -1,258 +1,307 @@
+/**
+ * @file tcp_client.c
+ * @brief Indexed lwIP RAW TCP client manager.
+ */
+
 #include "tcp_client.h"
 
-#include "FreeRTOS.h"
+#include "../Core/Inc/main.h"
-#include "task.h"
+#include "../Drivers/LwIP/src/include/lwip/ip_addr.h"
-#include "queue.h"
+#include "../Drivers/LwIP/src/include/lwip/pbuf.h"
-#include "lwip/api.h"
+#include "../Drivers/LwIP/src/include/lwip/tcp.h"
-#include "lwip/ip_addr.h"
-#include "lwip/tcp.h"
-#include "lwip/tcpip.h"
 
-#include "app_runtime.h"
+#include <string.h>
-#include "config.h"
-#include "debug_log.h"
-#include "ethernetif.h"
-#include "route_msg.h"
 
-#define TCP_CLIENT_CONNECT_TIMEOUT_MS 500
+typedef struct {
-#define TCP_CLIENT_RECONNECT_INTERVAL_MS 3000u
-#define TCP_CLIENT_STOP_POLL_MS       50u
-
-static BaseType_t tcp_client_stop_requested(void)
-{
-    return (app_network_task_stop_requested() != pdFALSE) ? pdTRUE : pdFALSE;
-}
-
-static BaseType_t tcp_client_delay_with_stop(uint32_t delay_ms)
-{
-    uint32_t remaining_ms = delay_ms;
-
-    while (remaining_ms > 0u) {
-        uint32_t slice_ms = (remaining_ms > TCP_CLIENT_STOP_POLL_MS) ? TCP_CLIENT_STOP_POLL_MS : remaining_ms;
-
-        if (tcp_client_stop_requested() != pdFALSE) {
-            return pdFALSE;
-        }
-
-        vTaskDelay(pdMS_TO_TICKS(slice_ms));
-        remaining_ms -= slice_ms;
-    }
-
-    return (tcp_client_stop_requested() == pdFALSE) ? pdTRUE : pdFALSE;
-}
-
-static void tcp_client_abort_and_delete(struct netconn *conn, uint8_t link_index)
-{
     struct tcp_pcb *pcb;
+    uint8_t rx_ring[TCP_CLIENT_RX_BUFFER_SIZE];
+    uint16_t rx_head;
+    uint16_t rx_tail;
+    uint32_t next_retry_ms;
+    uint8_t index;
+    tcp_client_instance_config_t config;
+    tcp_client_status_t status;
+} tcp_client_ctx_t;
 
-    if (conn == NULL) {
+static tcp_client_ctx_t g_clients[TCP_CLIENT_INSTANCE_COUNT];
+
+static uint16_t ring_free(uint16_t head, uint16_t tail, uint16_t size)
+{
+    return (head >= tail) ? (uint16_t)(size - head + tail - 1u) : (uint16_t)(tail - head - 1u);
+}
+
+static err_t tcp_client_on_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+    tcp_client_ctx_t *ctx = (tcp_client_ctx_t *)arg;
+    struct pbuf *q;
+
+    if (ctx == NULL) {
+        if (p != NULL) {
+            pbuf_free(p);
+        }
+        return ERR_ARG;
+    }
+    if (err != ERR_OK) {
+        if (p != NULL) {
+            pbuf_free(p);
+        }
+        return err;
+    }
+    if (p == NULL) {
+        tcp_arg(pcb, NULL);
+        tcp_recv(pcb, NULL);
+        tcp_sent(pcb, NULL);
+        tcp_err(pcb, NULL);
+        if (tcp_close(pcb) != ERR_OK) {
+            tcp_abort(pcb);
+        }
+        ctx->pcb = NULL;
+        ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
+        ctx->next_retry_ms = HAL_GetTick() + ctx->config.reconnect_interval_ms;
+        return ERR_OK;
+    }
+
+    for (q = p; q != NULL; q = q->next) {
+        const uint8_t *src = (const uint8_t *)q->payload;
+        for (uint16_t i = 0; i < q->len; ++i) {
+            if (ring_free(ctx->rx_head, ctx->rx_tail, TCP_CLIENT_RX_BUFFER_SIZE) == 0u) {
+                ctx->status.errors++;
+                break;
+            }
+            ctx->rx_ring[ctx->rx_head] = src[i];
+            ctx->rx_head = (uint16_t)((ctx->rx_head + 1u) % TCP_CLIENT_RX_BUFFER_SIZE);
+            ctx->status.rx_bytes++;
+        }
+    }
+
+    tcp_recved(pcb, p->tot_len);
+    pbuf_free(p);
+    return ERR_OK;
+}
+
+static err_t tcp_client_on_sent(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+    tcp_client_ctx_t *ctx = (tcp_client_ctx_t *)arg;
+    (void)pcb;
+    if (ctx != NULL) {
+        ctx->status.tx_bytes += len;
+    }
+    return ERR_OK;
+}
+
+static void tcp_client_on_err(void *arg, err_t err)
+{
+    tcp_client_ctx_t *ctx = (tcp_client_ctx_t *)arg;
+    if (ctx == NULL) {
         return;
     }
+    ctx->pcb = NULL;
+    ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
+    ctx->status.errors++;
+    ctx->next_retry_ms = HAL_GetTick() + ctx->config.reconnect_interval_ms;
+    (void)err;
+}
 
-    pcb = conn->pcb.tcp;
+static err_t tcp_client_on_connected(void *arg, struct tcp_pcb *pcb, err_t err)
-    if (pcb != NULL) {
+{
-        LOCK_TCPIP_CORE();
+    tcp_client_ctx_t *ctx = (tcp_client_ctx_t *)arg;
-        pcb = conn->pcb.tcp;
+
-        if (pcb != NULL) {
+    if (ctx == NULL) {
+        return ERR_ARG;
+    }
+    if (err != ERR_OK) {
+        ctx->pcb = NULL;
+        ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
+        ctx->status.errors++;
+        ctx->next_retry_ms = HAL_GetTick() + ctx->config.reconnect_interval_ms;
+        return err;
+    }
+
+    ctx->pcb = pcb;
+    ctx->status.state = TCP_CLIENT_STATE_CONNECTED;
+    tcp_nagle_disable(pcb);
+    tcp_arg(pcb, ctx);
+    tcp_recv(pcb, tcp_client_on_recv);
+    tcp_sent(pcb, tcp_client_on_sent);
+    tcp_err(pcb, tcp_client_on_err);
+    return ERR_OK;
+}
+
+int tcp_client_init_all(void)
+{
+    memset(g_clients, 0, sizeof(g_clients));
+    for (uint8_t i = 0; i < TCP_CLIENT_INSTANCE_COUNT; ++i) {
+        g_clients[i].index = i;
+        g_clients[i].status.state = TCP_CLIENT_STATE_IDLE;
+        g_clients[i].config.reconnect_interval_ms = TCP_CLIENT_RECONNECT_DELAY_MS;
+        g_clients[i].config.auto_reconnect = true;
+    }
+    return 0;
+}
+
+int tcp_client_config(uint8_t instance, const tcp_client_instance_config_t *config)
+{
+    if (instance >= TCP_CLIENT_INSTANCE_COUNT || config == NULL) {
+        return -1;
+    }
+    g_clients[instance].config = *config;
+    return 0;
+}
+
+int tcp_client_connect(uint8_t instance)
+{
+    struct tcp_pcb *pcb;
+    ip_addr_t remote_addr;
+    err_t err;
+    tcp_client_ctx_t *ctx;
+
+    if (instance >= TCP_CLIENT_INSTANCE_COUNT) {
+        return -1;
+    }
+    ctx = &g_clients[instance];
+    if (!ctx->config.enabled) {
+        return 0;
+    }
+    if (ctx->pcb != NULL) {
+        return 0;
+    }
+
+    pcb = tcp_new_ip_type(IPADDR_TYPE_V4);
+    if (pcb == NULL) {
+        ctx->status.errors++;
+        ctx->status.state = TCP_CLIENT_STATE_ERROR;
+        return -1;
+    }
+    if (ctx->config.local_port != 0u) {
+        err = tcp_bind(pcb, IP_ANY_TYPE, ctx->config.local_port);
+        if (err != ERR_OK) {
             tcp_abort(pcb);
-            conn->pcb.tcp = NULL;
+            ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
-            conn->state = NETCONN_NONE;
+            ctx->status.errors++;
-            debug_log_printf("[CLI] idx=%u abort-close\r\n", (unsigned int)link_index);
+            ctx->next_retry_ms = HAL_GetTick() + ctx->config.reconnect_interval_ms;
+            return -1;
         }
-        UNLOCK_TCPIP_CORE();
     }
 
-    netconn_delete(conn);
+    IP_ADDR4(&remote_addr,
-}
+             ctx->config.remote_ip[0],
+             ctx->config.remote_ip[1],
+             ctx->config.remote_ip[2],
+             ctx->config.remote_ip[3]);
 
-static err_t tcp_client_worker(struct netconn *conn, uint8_t link_index)
+    ctx->status.state = TCP_CLIENT_STATE_CONNECTING;
-{
+    tcp_arg(pcb, ctx);
-    struct netbuf *buf;
+    tcp_err(pcb, tcp_client_on_err);
-    const device_config_t *cfg = config_get();
+    err = tcp_connect(pcb, &remote_addr, ctx->config.remote_port, tcp_client_on_connected);
-    uint8_t uart_endpoint = config_uart_index_to_endpoint(cfg->links[link_index].uart);
-    uint8_t src_endpoint = config_link_index_to_endpoint(link_index);
-    err_t err;
-    route_msg_t *tx_msg;
-    route_send_result_t route_result;
-
-    netconn_set_recvtimeout(conn, 10);
-
-    for (;;) {
-        if (tcp_client_stop_requested() != pdFALSE) {
-            return ERR_CLSD;
-        }
-
-        err = netconn_recv(conn, &buf);
-        if (err == ERR_OK) {
-            do {
-                void *data;
-                uint16_t len;
-                netbuf_data(buf, &data, &len);
-                route_result = route_send(xTcpRxQueue,
-                                          src_endpoint,
-                                          uart_endpoint,
-                                          (link_index == CONFIG_LINK_C1) ? ROUTE_CONN_C1 : ROUTE_CONN_C2,
-                                          (const uint8_t *)data,
-                                          len,
-                                          pdMS_TO_TICKS(10));
-                if (route_result != ROUTE_SEND_OK) {
-                    debug_log_printf("[CLI] idx=%u rx-route-fail rc=%s len=%u\r\n",
-                                     (unsigned int)link_index,
-                                     route_send_result_to_str(route_result),
-                                     (unsigned int)len);
-                    netbuf_delete(buf);
-                    return ERR_CLSD;
-                }
-            } while (netbuf_next(buf) >= 0);
-            netbuf_delete(buf);
-        } else if (err == ERR_TIMEOUT) {
-            if (tcp_client_stop_requested() != pdFALSE) {
-                return ERR_CLSD;
-            }
-        } else {
-            return err;
-        }
-
-        while (xQueueReceive(xLinkTxQueues[link_index], &tx_msg, 0) == pdPASS) {
-            if (tcp_client_stop_requested() != pdFALSE) {
-                route_msg_free(tx_msg);
-                return ERR_CLSD;
-            }
-            err = netconn_write(conn, tx_msg->data, tx_msg->len, NETCONN_COPY);
-            route_msg_free(tx_msg);
     if (err != ERR_OK) {
-                return err;
+        tcp_err(pcb, NULL);
-            }
+        tcp_abort(pcb);
-        }
+        ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
+        ctx->status.errors++;
+        ctx->next_retry_ms = HAL_GetTick() + ctx->config.reconnect_interval_ms;
+        return -1;
     }
 
+    ctx->pcb = pcb;
+    return 0;
 }
 
-static void tcp_client_task(uint8_t link_index)
+int tcp_client_disconnect(uint8_t instance)
+{
+    tcp_client_ctx_t *ctx;
+
+    if (instance >= TCP_CLIENT_INSTANCE_COUNT) {
+        return -1;
+    }
+    ctx = &g_clients[instance];
+    if (ctx->pcb != NULL) {
+        tcp_arg(ctx->pcb, NULL);
+        tcp_recv(ctx->pcb, NULL);
+        tcp_sent(ctx->pcb, NULL);
+        tcp_err(ctx->pcb, NULL);
+        tcp_abort(ctx->pcb);
+        ctx->pcb = NULL;
+    }
+    ctx->status.state = TCP_CLIENT_STATE_DISCONNECTED;
+    ctx->rx_head = 0u;
+    ctx->rx_tail = 0u;
+    return 0;
+}
+
+int tcp_client_send(uint8_t instance, const uint8_t *data, uint16_t len)
 {
-    const device_config_t *cfg;
-    struct netconn *conn;
-    ip_addr_t remote_ip;
-    uint32_t delay_ms;
     err_t err;
-    uint8_t first_connect_deferred;
+    tcp_client_ctx_t *ctx;
 
-    netconn_thread_init();
+    if (instance >= TCP_CLIENT_INSTANCE_COUNT || data == NULL || len == 0u) {
-    first_connect_deferred = (link_index == CONFIG_LINK_C1) ? 1u : 0u;
+        return -1;
-
-    for (;;) {
-        if (tcp_client_stop_requested() != pdFALSE) {
-            break;
     }
-
+    ctx = &g_clients[instance];
-        while ((g_netif_ready == pdFALSE) || (ethernetif_link_is_up() == 0u)) {
+    if (ctx->pcb == NULL) {
-            if (tcp_client_stop_requested() != pdFALSE) {
+        return -1;
-                goto exit_task;
     }
-            vTaskDelay(pdMS_TO_TICKS(100));
+    if (tcp_sndbuf(ctx->pcb) < len) {
+        return 0;
     }
-
+    err = tcp_write(ctx->pcb, data, len, TCP_WRITE_FLAG_COPY);
-        cfg = config_get();
-        if (cfg->links[link_index].enabled == 0u) {
-            if (tcp_client_stop_requested() != pdFALSE) {
-                break;
-            }
-            if (tcp_client_delay_with_stop(500u) == pdFALSE) {
-                break;
-            }
-            continue;
-        }
-
-        delay_ms = TCP_CLIENT_RECONNECT_INTERVAL_MS;
-
-        if (first_connect_deferred != 0u) {
-            first_connect_deferred = 0u;
-            debug_log_write("[CLI] C1 first-connect defer\r\n");
-            if (tcp_client_delay_with_stop(delay_ms) == pdFALSE) {
-                break;
-            }
-            continue;
-        }
-
-        conn = netconn_new(NETCONN_TCP);
-        if (conn == NULL) {
-            if (tcp_client_delay_with_stop(delay_ms) == pdFALSE) {
-                break;
-            }
-            continue;
-        }
-
-        if (cfg->links[link_index].local_port != 0u) {
-            err = netconn_bind(conn, IP_ADDR_ANY, cfg->links[link_index].local_port);
     if (err != ERR_OK) {
-                debug_log_printf("[CLI] idx=%u bind-fail err=%d lport=%u\r\n",
+        ctx->status.errors++;
-                                 (unsigned int)link_index,
+        return -1;
-                                 (int)err,
-                                 (unsigned int)cfg->links[link_index].local_port);
-                netconn_delete(conn);
-                if (tcp_client_delay_with_stop(delay_ms) == pdFALSE) {
-                    break;
     }
+    err = tcp_output(ctx->pcb);
+    if (err != ERR_OK) {
+        ctx->status.errors++;
+        return -1;
+    }
+    return (int)len;
+}
+
+int tcp_client_recv(uint8_t instance, uint8_t *data, uint16_t max_len)
+{
+    uint16_t copied = 0u;
+    tcp_client_ctx_t *ctx;
+
+    if (instance >= TCP_CLIENT_INSTANCE_COUNT || data == NULL || max_len == 0u) {
+        return -1;
+    }
+    ctx = &g_clients[instance];
+    while (copied < max_len && ctx->rx_tail != ctx->rx_head) {
+        data[copied++] = ctx->rx_ring[ctx->rx_tail];
+        ctx->rx_tail = (uint16_t)((ctx->rx_tail + 1u) % TCP_CLIENT_RX_BUFFER_SIZE);
+    }
+    return (int)copied;
+}
+
+bool tcp_client_is_connected(uint8_t instance)
+{
+    return (instance < TCP_CLIENT_INSTANCE_COUNT) &&
+           (g_clients[instance].pcb != NULL) &&
+           (g_clients[instance].status.state == TCP_CLIENT_STATE_CONNECTED);
+}
+
+void tcp_client_get_status(uint8_t instance, tcp_client_status_t *status)
+{
+    if (instance < TCP_CLIENT_INSTANCE_COUNT && status != NULL) {
+        *status = g_clients[instance].status;
+    }
+}
+
+void tcp_client_poll(void)
+{
+    uint32_t now = HAL_GetTick();
+
+    for (uint8_t i = 0; i < TCP_CLIENT_INSTANCE_COUNT; ++i) {
+        tcp_client_ctx_t *ctx = &g_clients[i];
+        if (!ctx->config.enabled || !ctx->config.auto_reconnect || tcp_client_is_connected(i)) {
             continue;
         }
+        if ((ctx->pcb != NULL) && (ctx->status.state == TCP_CLIENT_STATE_CONNECTING)) {
+            continue;
         }
-
+        if (now >= ctx->next_retry_ms) {
-        IP_ADDR4(&remote_ip,
+            ctx->status.reconnect_count++;
-                 cfg->links[link_index].remote_ip[0],
+            ctx->next_retry_ms = now + ctx->config.reconnect_interval_ms;
-                 cfg->links[link_index].remote_ip[1],
+            (void)tcp_client_connect(i);
-                 cfg->links[link_index].remote_ip[2],
-                 cfg->links[link_index].remote_ip[3]);
-
-        netconn_set_recvtimeout(conn, TCP_CLIENT_CONNECT_TIMEOUT_MS);
-        err = netconn_connect(conn, &remote_ip, cfg->links[link_index].remote_port);
-        if (err == ERR_OK) {
-            debug_log_printf("[CLI] idx=%u connect-ok\r\n", (unsigned int)link_index);
-            (void)tcp_client_worker(conn, link_index);
-        } else {
-            if (err == ERR_TIMEOUT) {
-                debug_log_printf("[CLI] idx=%u connect-timeout ms=%u rip=%u.%u.%u.%u rport=%u\r\n",
-                                 (unsigned int)link_index,
-                                 (unsigned int)TCP_CLIENT_CONNECT_TIMEOUT_MS,
-                                 (unsigned int)cfg->links[link_index].remote_ip[0],
-                                 (unsigned int)cfg->links[link_index].remote_ip[1],
-                                 (unsigned int)cfg->links[link_index].remote_ip[2],
-                                 (unsigned int)cfg->links[link_index].remote_ip[3],
-                                 (unsigned int)cfg->links[link_index].remote_port);
-            } else {
-                debug_log_printf("[CLI] idx=%u connect-fail err=%d rip=%u.%u.%u.%u rport=%u\r\n",
-                                 (unsigned int)link_index,
-                                 (int)err,
-                                 (unsigned int)cfg->links[link_index].remote_ip[0],
-                                 (unsigned int)cfg->links[link_index].remote_ip[1],
-                                 (unsigned int)cfg->links[link_index].remote_ip[2],
-                                 (unsigned int)cfg->links[link_index].remote_ip[3],
-                                 (unsigned int)cfg->links[link_index].remote_port);
         }
     }
-
-        tcp_client_abort_and_delete(conn, link_index);
-        if (tcp_client_stop_requested() != pdFALSE) {
-            break;
-        }
-        if (tcp_client_delay_with_stop(delay_ms) == pdFALSE) {
-            break;
-        }
-    }
-
-exit_task:
-    netconn_thread_cleanup();
-    app_on_network_task_exit(xTaskGetCurrentTaskHandle());
-    vTaskDelete(NULL);
-}
-
-void TcpCliTask_C1(void *argument)
-{
-    (void)argument;
-    tcp_client_task(CONFIG_LINK_C1);
-}
-
-void TcpCliTask_C2(void *argument)
-{
-    (void)argument;
-    tcp_client_task(CONFIG_LINK_C2);
 }

App/tcp_client.h

@@ -1,15 +1,59 @@
-#ifndef TCP_CLIENT_H
+/**
-#define TCP_CLIENT_H
+ * @file tcp_client.h
+ * @brief Indexed lwIP RAW TCP client manager.
+ */
+
+#ifndef __TCP_CLIENT_H__
+#define __TCP_CLIENT_H__
+
+#include <stdbool.h>
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-void TcpCliTask_C1(void *argument);
+#define TCP_CLIENT_INSTANCE_COUNT      2u
-void TcpCliTask_C2(void *argument);
+#define TCP_CLIENT_RX_BUFFER_SIZE      512u
+#define TCP_CLIENT_RECONNECT_DELAY_MS  3000u
+
+typedef enum {
+    TCP_CLIENT_STATE_IDLE = 0,
+    TCP_CLIENT_STATE_CONNECTING,
+    TCP_CLIENT_STATE_CONNECTED,
+    TCP_CLIENT_STATE_DISCONNECTED,
+    TCP_CLIENT_STATE_ERROR
+} tcp_client_state_t;
+
+typedef struct {
+    uint8_t remote_ip[4];
+    uint16_t local_port;
+    uint16_t remote_port;
+    uint16_t reconnect_interval_ms;
+    bool enabled;
+    bool auto_reconnect;
+} tcp_client_instance_config_t;
+
+typedef struct {
+    tcp_client_state_t state;
+    uint32_t rx_bytes;
+    uint32_t tx_bytes;
+    uint32_t reconnect_count;
+    uint32_t errors;
+} tcp_client_status_t;
+
+int tcp_client_init_all(void);
+int tcp_client_config(uint8_t instance, const tcp_client_instance_config_t *config);
+int tcp_client_connect(uint8_t instance);
+int tcp_client_disconnect(uint8_t instance);
+int tcp_client_send(uint8_t instance, const uint8_t *data, uint16_t len);
+int tcp_client_recv(uint8_t instance, uint8_t *data, uint16_t max_len);
+bool tcp_client_is_connected(uint8_t instance);
+void tcp_client_get_status(uint8_t instance, tcp_client_status_t *status);
+void tcp_client_poll(void);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif
+#endif /* __TCP_CLIENT_H__ */

App/tcp_server.c

@@ -1,185 +1,273 @@
+/**
+ * @file tcp_server.c
+ * @brief Indexed lwIP RAW TCP server manager.
+ */
+
 #include "tcp_server.h"
 
-#include "FreeRTOS.h"
+#include "../Drivers/LwIP/src/include/lwip/pbuf.h"
-#include "task.h"
+#include "../Drivers/LwIP/src/include/lwip/tcp.h"
-#include "queue.h"
-#include "lwip/api.h"
-#include "lwip/ip_addr.h"
 
-#include "app_runtime.h"
+#include "SEGGER_RTT.h"
-#include "config.h"
-#include "debug_log.h"
-#include "route_msg.h"
 
-#define TCP_SERVER_ACCEPT_TIMEOUT_MS 100
+#include <string.h>
-#define TCP_SERVER_STOP_POLL_MS      50u
 
-static BaseType_t tcp_server_stop_requested(void)
+typedef struct {
+    struct tcp_pcb *listen_pcb;
+    struct tcp_pcb *client_pcb;
+    uint8_t rx_ring[TCP_SERVER_RX_BUFFER_SIZE];
+    uint16_t rx_head;
+    uint16_t rx_tail;
+    uint8_t index;
+    tcp_server_instance_config_t config;
+    tcp_server_status_t status;
+} tcp_server_ctx_t;
+
+static tcp_server_ctx_t g_servers[TCP_SERVER_INSTANCE_COUNT];
+
+static uint16_t ring_free(uint16_t head, uint16_t tail, uint16_t size)
 {
-    return (app_network_task_stop_requested() != pdFALSE) ? pdTRUE : pdFALSE;
+    return (head >= tail) ? (uint16_t)(size - head + tail - 1u) : (uint16_t)(tail - head - 1u);
 }
 
-static BaseType_t tcp_server_delay_with_stop(uint32_t delay_ms)
+static err_t tcp_server_on_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
 {
-    uint32_t remaining_ms = delay_ms;
+    tcp_server_ctx_t *ctx = (tcp_server_ctx_t *)arg;
+    struct pbuf *q;
 
-    while (remaining_ms > 0u) {
+    if (ctx == NULL) {
-        uint32_t slice_ms = (remaining_ms > TCP_SERVER_STOP_POLL_MS) ? TCP_SERVER_STOP_POLL_MS : remaining_ms;
+        if (p != NULL) {
-
+            pbuf_free(p);
-        if (tcp_server_stop_requested() != pdFALSE) {
-            return pdFALSE;
         }
-
+        return ERR_ARG;
-        vTaskDelay(pdMS_TO_TICKS(slice_ms));
-        remaining_ms -= slice_ms;
     }
-
-    return (tcp_server_stop_requested() == pdFALSE) ? pdTRUE : pdFALSE;
-}
-
-static err_t tcp_server_worker(struct netconn *conn, uint8_t link_index)
-{
-    struct netbuf *buf;
-    const device_config_t *cfg = config_get();
-    uint8_t uart_endpoint = config_uart_index_to_endpoint(cfg->links[link_index].uart);
-    uint8_t src_endpoint = config_link_index_to_endpoint(link_index);
-    err_t err;
-    route_msg_t *tx_msg;
-    route_send_result_t route_result;
-
-    netconn_set_recvtimeout(conn, 10);
-
-    for (;;) {
-        if (tcp_server_stop_requested() != pdFALSE) {
-            return ERR_CLSD;
-        }
-
-        err = netconn_recv(conn, &buf);
-        if (err == ERR_OK) {
-            do {
-                void *data;
-                uint16_t len;
-                netbuf_data(buf, &data, &len);
-                route_result = route_send(xTcpRxQueue,
-                                          src_endpoint,
-                                          uart_endpoint,
-                                          (link_index == CONFIG_LINK_S1) ? ROUTE_CONN_S1 : ROUTE_CONN_S2,
-                                          (const uint8_t *)data,
-                                          len,
-                                          pdMS_TO_TICKS(10));
-                if (route_result != ROUTE_SEND_OK) {
-                    debug_log_printf("[SRV] idx=%u rx-route-fail rc=%s len=%u\r\n",
-                                     (unsigned int)link_index,
-                                     route_send_result_to_str(route_result),
-                                     (unsigned int)len);
-                    netbuf_delete(buf);
-                    return ERR_CLSD;
-                }
-            } while (netbuf_next(buf) >= 0);
-            netbuf_delete(buf);
-        } else if (err == ERR_TIMEOUT) {
-            if (tcp_server_stop_requested() != pdFALSE) {
-                return ERR_CLSD;
-            }
-        } else {
-            break;
-        }
-
-        while (xQueueReceive(xLinkTxQueues[link_index], &tx_msg, 0) == pdPASS) {
-            if (tcp_server_stop_requested() != pdFALSE) {
-                route_msg_free(tx_msg);
-                return ERR_CLSD;
-            }
-            err = netconn_write(conn, tx_msg->data, tx_msg->len, NETCONN_COPY);
-            route_msg_free(tx_msg);
     if (err != ERR_OK) {
+        if (p != NULL) {
+            pbuf_free(p);
+        }
         return err;
     }
+    if (p == NULL) {
+        tcp_arg(pcb, NULL);
+        tcp_recv(pcb, NULL);
+        tcp_sent(pcb, NULL);
+        tcp_err(pcb, NULL);
+        if (tcp_close(pcb) != ERR_OK) {
+            tcp_abort(pcb);
+        }
+        ctx->client_pcb = NULL;
+        ctx->status.state = ctx->config.enabled ? TCP_SERVER_STATE_LISTENING : TCP_SERVER_STATE_IDLE;
+        return ERR_OK;
+    }
+
+    for (q = p; q != NULL; q = q->next) {
+        const uint8_t *src = (const uint8_t *)q->payload;
+        for (uint16_t i = 0; i < q->len; ++i) {
+            if (ring_free(ctx->rx_head, ctx->rx_tail, TCP_SERVER_RX_BUFFER_SIZE) == 0u) {
+                ctx->status.errors++;
+                break;
+            }
+            ctx->rx_ring[ctx->rx_head] = src[i];
+            ctx->rx_head = (uint16_t)((ctx->rx_head + 1u) % TCP_SERVER_RX_BUFFER_SIZE);
+            ctx->status.rx_bytes++;
         }
     }
 
-    return err;
+    tcp_recved(pcb, p->tot_len);
+    pbuf_free(p);
+    return ERR_OK;
 }
 
-static void tcp_server_task(uint8_t link_index)
+static err_t tcp_server_on_sent(void *arg, struct tcp_pcb *pcb, u16_t len)
 {
-    const device_config_t *cfg;
+    tcp_server_ctx_t *ctx = (tcp_server_ctx_t *)arg;
-    struct netconn *listener;
+    (void)pcb;
-    struct netconn *newconn;
+    if (ctx != NULL) {
-
+        ctx->status.tx_bytes += len;
-    netconn_thread_init();
+    }
-
+    return ERR_OK;
-    for (;;) {
-        if (tcp_server_stop_requested() != pdFALSE) {
-            break;
 }
 
-        while (g_netif_ready == pdFALSE) {
+static void tcp_server_on_err(void *arg, err_t err)
-            if (tcp_server_stop_requested() != pdFALSE) {
-                goto exit_task;
-            }
-            vTaskDelay(pdMS_TO_TICKS(100));
-        }
-
-        cfg = config_get();
-        if (cfg->links[link_index].enabled == 0u) {
-            if (tcp_server_stop_requested() != pdFALSE) {
-                break;
-            }
-            if (tcp_server_delay_with_stop(500u) == pdFALSE) {
-                break;
-            }
-            continue;
-        }
-
-        listener = netconn_new(NETCONN_TCP);
-        if (listener == NULL) {
-            if (tcp_server_delay_with_stop(500u) == pdFALSE) {
-                break;
-            }
-            continue;
-        }
-
-        netconn_set_recvtimeout(listener, TCP_SERVER_ACCEPT_TIMEOUT_MS);
-
-        if (netconn_bind(listener, IP_ADDR_ANY, cfg->links[link_index].local_port) != ERR_OK ||
-            netconn_listen(listener) != ERR_OK) {
-            netconn_delete(listener);
-            if (tcp_server_delay_with_stop(500u) == pdFALSE) {
-                break;
-            }
-            continue;
-        }
-
-        for (;;) {
-            if (tcp_server_stop_requested() != pdFALSE || cfg->links[link_index].enabled == 0u) {
-                break;
-            }
-            if (netconn_accept(listener, &newconn) == ERR_OK) {
-                tcp_server_worker(newconn, link_index);
-                netconn_close(newconn);
-                netconn_delete(newconn);
-            }
-        }
-
-        netconn_close(listener);
-        netconn_delete(listener);
-    }
-
-exit_task:
-    netconn_thread_cleanup();
-    app_on_network_task_exit(xTaskGetCurrentTaskHandle());
-    vTaskDelete(NULL);
-}
-
-void TcpSrvTask_S1(void *argument)
 {
-    (void)argument;
+    tcp_server_ctx_t *ctx = (tcp_server_ctx_t *)arg;
-    tcp_server_task(CONFIG_LINK_S1);
+    if (ctx == NULL) {
+        return;
+    }
+    ctx->client_pcb = NULL;
+    ctx->status.state = ctx->config.enabled ? TCP_SERVER_STATE_LISTENING : TCP_SERVER_STATE_IDLE;
+    ctx->status.errors++;
+    SEGGER_RTT_printf(0, "TCP server[%u] connection error=%d\r\n", ctx->index, (int)err);
 }
 
-void TcpSrvTask_S2(void *argument)
+static err_t tcp_server_on_accept(void *arg, struct tcp_pcb *newpcb, err_t err)
 {
-    (void)argument;
+    tcp_server_ctx_t *ctx = (tcp_server_ctx_t *)arg;
-    tcp_server_task(CONFIG_LINK_S2);
+
+    if (ctx == NULL || err != ERR_OK) {
+        return (ctx == NULL) ? ERR_ARG : err;
+    }
+    if (ctx->client_pcb != NULL) {
+        tcp_abort(newpcb);
+        return ERR_ABRT;
+    }
+
+    ctx->client_pcb = newpcb;
+    ctx->status.state = TCP_SERVER_STATE_CONNECTED;
+    ctx->status.connections++;
+    tcp_nagle_disable(newpcb);
+    tcp_arg(newpcb, ctx);
+    tcp_recv(newpcb, tcp_server_on_recv);
+    tcp_sent(newpcb, tcp_server_on_sent);
+    tcp_err(newpcb, tcp_server_on_err);
+    return ERR_OK;
+}
+
+int tcp_server_init_all(void)
+{
+    memset(g_servers, 0, sizeof(g_servers));
+    for (uint8_t i = 0; i < TCP_SERVER_INSTANCE_COUNT; ++i) {
+        g_servers[i].index = i;
+        g_servers[i].status.state = TCP_SERVER_STATE_IDLE;
+    }
+    return 0;
+}
+
+int tcp_server_config(uint8_t instance, const tcp_server_instance_config_t *config)
+{
+    if (instance >= TCP_SERVER_INSTANCE_COUNT || config == NULL) {
+        return -1;
+    }
+    g_servers[instance].config = *config;
+    return 0;
+}
+
+int tcp_server_start(uint8_t instance)
+{
+    struct tcp_pcb *pcb;
+    err_t err;
+    tcp_server_ctx_t *ctx;
+
+    if (instance >= TCP_SERVER_INSTANCE_COUNT) {
+        return -1;
+    }
+    ctx = &g_servers[instance];
+    if (!ctx->config.enabled) {
+        ctx->status.state = TCP_SERVER_STATE_IDLE;
+        return 0;
+    }
+    if (ctx->listen_pcb != NULL) {
+        return 0;
+    }
+
+    pcb = tcp_new_ip_type(IPADDR_TYPE_V4);
+    if (pcb == NULL) {
+        ctx->status.errors++;
+        return -1;
+    }
+
+    err = tcp_bind(pcb, IP_ANY_TYPE, ctx->config.port);
+    if (err != ERR_OK) {
+        tcp_abort(pcb);
+        ctx->status.errors++;
+        return -1;
+    }
+
+    ctx->listen_pcb = tcp_listen_with_backlog(pcb, 1);
+    if (ctx->listen_pcb == NULL) {
+        ctx->status.errors++;
+        return -1;
+    }
+
+    tcp_arg(ctx->listen_pcb, ctx);
+    tcp_accept(ctx->listen_pcb, tcp_server_on_accept);
+    ctx->status.state = TCP_SERVER_STATE_LISTENING;
+    return 0;
+}
+
+int tcp_server_stop(uint8_t instance)
+{
+    tcp_server_ctx_t *ctx;
+
+    if (instance >= TCP_SERVER_INSTANCE_COUNT) {
+        return -1;
+    }
+    ctx = &g_servers[instance];
+
+    if (ctx->client_pcb != NULL) {
+        tcp_arg(ctx->client_pcb, NULL);
+        tcp_recv(ctx->client_pcb, NULL);
+        tcp_sent(ctx->client_pcb, NULL);
+        tcp_err(ctx->client_pcb, NULL);
+        tcp_abort(ctx->client_pcb);
+        ctx->client_pcb = NULL;
+    }
+    if (ctx->listen_pcb != NULL) {
+        tcp_arg(ctx->listen_pcb, NULL);
+        tcp_accept(ctx->listen_pcb, NULL);
+        tcp_close(ctx->listen_pcb);
+        ctx->listen_pcb = NULL;
+    }
+
+    ctx->status.state = TCP_SERVER_STATE_IDLE;
+    ctx->rx_head = 0u;
+    ctx->rx_tail = 0u;
+    return 0;
+}
+
+int tcp_server_send(uint8_t instance, const uint8_t *data, uint16_t len)
+{
+    err_t err;
+    tcp_server_ctx_t *ctx;
+
+    if (instance >= TCP_SERVER_INSTANCE_COUNT || data == NULL || len == 0u) {
+        return -1;
+    }
+    ctx = &g_servers[instance];
+    if (ctx->client_pcb == NULL) {
+        return -1;
+    }
+    if (tcp_sndbuf(ctx->client_pcb) < len) {
+        return 0;
+    }
+
+    err = tcp_write(ctx->client_pcb, data, len, TCP_WRITE_FLAG_COPY);
+    if (err != ERR_OK) {
+        ctx->status.errors++;
+        return -1;
+    }
+    err = tcp_output(ctx->client_pcb);
+    if (err != ERR_OK) {
+        ctx->status.errors++;
+        return -1;
+    }
+    return (int)len;
+}
+
+int tcp_server_recv(uint8_t instance, uint8_t *data, uint16_t max_len)
+{
+    uint16_t copied = 0u;
+    tcp_server_ctx_t *ctx;
+
+    if (instance >= TCP_SERVER_INSTANCE_COUNT || data == NULL || max_len == 0u) {
+        return -1;
+    }
+    ctx = &g_servers[instance];
+    while (copied < max_len && ctx->rx_tail != ctx->rx_head) {
+        data[copied++] = ctx->rx_ring[ctx->rx_tail];
+        ctx->rx_tail = (uint16_t)((ctx->rx_tail + 1u) % TCP_SERVER_RX_BUFFER_SIZE);
+    }
+    return (int)copied;
+}
+
+bool tcp_server_is_connected(uint8_t instance)
+{
+    return (instance < TCP_SERVER_INSTANCE_COUNT) && (g_servers[instance].client_pcb != NULL);
+}
+
+void tcp_server_get_status(uint8_t instance, tcp_server_status_t *status)
+{
+    if (instance < TCP_SERVER_INSTANCE_COUNT && status != NULL) {
+        *status = g_servers[instance].status;
+    }
 }

App/tcp_server.h

@@ -1,15 +1,52 @@
-#ifndef TCP_SERVER_H
+/**
-#define TCP_SERVER_H
+ * @file tcp_server.h
+ * @brief Indexed lwIP RAW TCP server manager.
+ */
+
+#ifndef __TCP_SERVER_H__
+#define __TCP_SERVER_H__
+
+#include <stdbool.h>
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-void TcpSrvTask_S1(void *argument);
+#define TCP_SERVER_INSTANCE_COUNT    2u
-void TcpSrvTask_S2(void *argument);
+#define TCP_SERVER_RX_BUFFER_SIZE    512u
+
+typedef enum {
+    TCP_SERVER_STATE_IDLE = 0,
+    TCP_SERVER_STATE_LISTENING,
+    TCP_SERVER_STATE_CONNECTED,
+    TCP_SERVER_STATE_ERROR
+} tcp_server_state_t;
+
+typedef struct {
+    uint16_t port;
+    bool enabled;
+} tcp_server_instance_config_t;
+
+typedef struct {
+    tcp_server_state_t state;
+    uint32_t rx_bytes;
+    uint32_t tx_bytes;
+    uint32_t connections;
+    uint32_t errors;
+} tcp_server_status_t;
+
+int tcp_server_init_all(void);
+int tcp_server_config(uint8_t instance, const tcp_server_instance_config_t *config);
+int tcp_server_start(uint8_t instance);
+int tcp_server_stop(uint8_t instance);
+int tcp_server_send(uint8_t instance, const uint8_t *data, uint16_t len);
+int tcp_server_recv(uint8_t instance, uint8_t *data, uint16_t max_len);
+bool tcp_server_is_connected(uint8_t instance);
+void tcp_server_get_status(uint8_t instance, tcp_server_status_t *status);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif
+#endif /* __TCP_SERVER_H__ */

App/uart_trans.c

@@ -1,24 +1,17 @@
+/**
+ * @file uart_trans.c
+ * @brief Bare-metal UART DMA/IDLE transport and MUX helpers.
+ */
+
 #include "uart_trans.h"
 
+#include "../Core/Inc/usart.h"
+
 #include <string.h>
 
-#include "FreeRTOS.h"
-#include "task.h"
-#include "usart.h"
-
-#include "app_runtime.h"
-#include "config.h"
-#include "debug_log.h"
-#include "route_msg.h"
-
 #define UART_MUX_SYNC  0x7Eu
 #define UART_MUX_TAIL  0x7Fu
 
-#define UART_NOTIFY_RX_U0   (1UL << 0)
-#define UART_NOTIFY_RX_U1   (1UL << 1)
-#define UART_NOTIFY_TX_U0   (1UL << 8)
-#define UART_NOTIFY_TX_U1   (1UL << 9)
-
 typedef struct {
     UART_HandleTypeDef *huart;
     uint8_t rx_dma_buffer[UART_RX_DMA_BUFFER_SIZE];
@@ -31,28 +24,15 @@ typedef struct {
     volatile uint16_t tx_head;
     volatile uint16_t tx_tail;
     volatile uint16_t tx_dma_len;
-    volatile uint8_t tx_busy;
+    volatile bool tx_busy;
-    volatile uint8_t tx_kick_fail_logged;
+    uart_config_t config;
+    uart_stats_t stats;
+    bool initialized;
+    bool running;
 } uart_channel_ctx_t;
 
 static uart_channel_ctx_t g_channels[UART_CHANNEL_MAX];
 
-const char *uart_trans_send_result_to_str(uart_trans_send_result_t result)
-{
-    switch (result) {
-    case UART_TRANS_SEND_OK:
-        return "ok";
-    case UART_TRANS_SEND_INVALID_INPUT:
-        return "invalid";
-    case UART_TRANS_SEND_RING_FULL:
-        return "full";
-    case UART_TRANS_SEND_KICK_FAILED:
-        return "kick";
-    default:
-        return "unknown";
-    }
-}
-
 static uint16_t ring_used(uint16_t head, uint16_t tail, uint16_t size)
 {
     return (head >= tail) ? (head - tail) : (size - tail + head);
@@ -63,41 +43,56 @@ static uint16_t ring_free(uint16_t head, uint16_t tail, uint16_t size)
     return (uint16_t)(size - ring_used(head, tail, size) - 1u);
 }
 
-static void process_rx_snapshot(uart_channel_t channel)
+static int apply_uart_config(uart_channel_t channel)
 {
     uart_channel_ctx_t *ctx = &g_channels[channel];
-    uint16_t dma_write_index = (uint16_t)(UART_RX_DMA_BUFFER_SIZE - __HAL_DMA_GET_COUNTER(ctx->huart->hdmarx));
+    if (ctx->huart == NULL) {
-
+        return -1;
-    if (dma_write_index >= UART_RX_DMA_BUFFER_SIZE) {
-        dma_write_index = 0u;
     }
 
+    if (ctx->running) {
+        HAL_UART_DMAStop(ctx->huart);
+        ctx->running = false;
+    }
+
+    ctx->huart->Init.BaudRate = ctx->config.baudrate;
+    ctx->huart->Init.WordLength = UART_WORDLENGTH_8B;
+    ctx->huart->Init.StopBits = UART_STOPBITS_1;
+    ctx->huart->Init.Parity = UART_PARITY_NONE;
+    return (HAL_UART_Init(ctx->huart) == HAL_OK) ? 0 : -1;
+}
+
+static void process_rx_snapshot(uart_channel_t channel, uint16_t dma_write_index)
+{
+    uart_channel_ctx_t *ctx = &g_channels[channel];
+
     while (ctx->rx_dma_read_index != dma_write_index) {
         uint16_t next_head = (uint16_t)((ctx->rx_head + 1u) % UART_RX_RING_BUFFER_SIZE);
         if (next_head == ctx->rx_tail) {
+            ctx->stats.errors++;
             break;
         }
+
         ctx->rx_ring[ctx->rx_head] = ctx->rx_dma_buffer[ctx->rx_dma_read_index];
         ctx->rx_head = next_head;
         ctx->rx_dma_read_index = (uint16_t)((ctx->rx_dma_read_index + 1u) % UART_RX_DMA_BUFFER_SIZE);
+        ctx->stats.rx_bytes++;
     }
 }
 
-static uart_trans_send_result_t kick_tx(uart_channel_t channel)
+static void kick_tx(uart_channel_t channel)
 {
     uart_channel_ctx_t *ctx = &g_channels[channel];
     uint16_t available;
     uint16_t chunk;
-    uint16_t tail;
-    uint16_t i;
 
-    if (ctx->tx_busy != 0u) {
+    if (!ctx->running || ctx->tx_busy) {
-        return UART_TRANS_SEND_OK;
+        return;
     }
 
     available = ring_used(ctx->tx_head, ctx->tx_tail, UART_TX_RING_BUFFER_SIZE);
     if (available == 0u) {
-        return UART_TRANS_SEND_OK;
+        return;
     }
 
     chunk = available;
@@ -105,294 +100,18 @@ static uart_trans_send_result_t kick_tx(uart_channel_t channel)
         chunk = UART_TX_DMA_BUFFER_SIZE;
     }
 
-    tail = ctx->tx_tail;
+    for (uint16_t i = 0; i < chunk; ++i) {
-    for (i = 0; i < chunk; ++i) {
+        ctx->tx_dma_buffer[i] = ctx->tx_ring[ctx->tx_tail];
-        ctx->tx_dma_buffer[i] = ctx->tx_ring[tail];
+        ctx->tx_tail = (uint16_t)((ctx->tx_tail + 1u) % UART_TX_RING_BUFFER_SIZE);
-        tail = (uint16_t)((tail + 1u) % UART_TX_RING_BUFFER_SIZE);
     }
 
+    ctx->tx_dma_len = chunk;
+    ctx->tx_busy = true;
+    ctx->stats.tx_packets++;
+
     if (HAL_UART_Transmit_DMA(ctx->huart, ctx->tx_dma_buffer, chunk) != HAL_OK) {
-        ctx->tx_dma_len = 0u;
+        ctx->tx_busy = false;
-        if (ctx->tx_kick_fail_logged == 0u) {
+        ctx->stats.errors++;
-            debug_log_printf("[UART] kick-fail ch=%u len=%u\r\n",
-                             (unsigned int)channel,
-                             (unsigned int)chunk);
-            ctx->tx_kick_fail_logged = 1u;
-        }
-        return UART_TRANS_SEND_KICK_FAILED;
-    }
-
-    ctx->tx_tail = tail;
-    ctx->tx_dma_len = chunk;
-    ctx->tx_busy = 1u;
-    ctx->tx_kick_fail_logged = 0u;
-    return UART_TRANS_SEND_OK;
-}
-
-static uint16_t uart_ring_available(uart_channel_t channel)
-{
-    return ring_used(g_channels[channel].rx_head, g_channels[channel].rx_tail, UART_RX_RING_BUFFER_SIZE);
-}
-
-static uint16_t uart_ring_read(uart_channel_t channel, uint8_t *data, uint16_t max_len)
-{
-    uart_channel_ctx_t *ctx = &g_channels[channel];
-    uint16_t copied = 0u;
-
-    while (copied < max_len && ctx->rx_tail != ctx->rx_head) {
-        data[copied++] = ctx->rx_ring[ctx->rx_tail];
-        ctx->rx_tail = (uint16_t)((ctx->rx_tail + 1u) % UART_RX_RING_BUFFER_SIZE);
-    }
-    return copied;
-}
-
-static bool uart_ring_peek_byte(uart_channel_t channel, uint16_t offset, uint8_t *data)
-{
-    uart_channel_ctx_t *ctx = &g_channels[channel];
-    uint16_t available = ring_used(ctx->rx_head, ctx->rx_tail, UART_RX_RING_BUFFER_SIZE);
-
-    if (data == NULL || offset >= available) {
-        return false;
-    }
-
-    *data = ctx->rx_ring[(ctx->rx_tail + offset) % UART_RX_RING_BUFFER_SIZE];
-    return true;
-}
-
-static void uart_ring_drop(uart_channel_t channel, uint16_t len)
-{
-    uart_channel_ctx_t *ctx = &g_channels[channel];
-
-    ctx->rx_tail = (uint16_t)((ctx->rx_tail + len) % UART_RX_RING_BUFFER_SIZE);
-}
-
-static void uart_route_raw_channel(uart_channel_t channel)
-{
-    const device_config_t *cfg = config_get();
-    uint8_t buffer[ROUTE_MSG_MAX_PAYLOAD];
-    uint16_t len;
-    uint8_t uart_endpoint = (channel == UART_CHANNEL_U1) ? ENDPOINT_UART3 : ENDPOINT_UART2;
-    uint32_t i;
-    route_send_result_t route_result;
-
-    len = uart_ring_read(channel, buffer, sizeof(buffer));
-    if (len == 0u) {
-        return;
-    }
-
-    for (i = 0; i < CONFIG_LINK_COUNT; ++i) {
-        if (cfg->links[i].enabled == 0u || cfg->links[i].uart != ((channel == UART_CHANNEL_U1) ? LINK_UART_U1 : LINK_UART_U0)) {
-            continue;
-        }
-
-        route_result = route_send(xLinkTxQueues[i],
-                                  uart_endpoint,
-                                  config_link_index_to_endpoint((uint8_t)i),
-                                  (channel == UART_CHANNEL_U1) ? ROUTE_CONN_UART3 : ROUTE_CONN_UART2,
-                                  buffer,
-                                  len,
-                                  pdMS_TO_TICKS(10));
-        if (route_result != ROUTE_SEND_OK) {
-            debug_log_printf("[UART] raw-route-fail idx=%u rc=%s len=%u\r\n",
-                             (unsigned int)i,
-                             route_send_result_to_str(route_result),
-                             (unsigned int)len);
-        }
-    }
-}
-
-static uart_trans_send_result_t uart_send_tcp_msg_chunk(route_msg_t *msg,
-                                                        uint16_t offset,
-                                                        uint16_t *accepted_len)
-{
-    uint8_t frame[ROUTE_MSG_MAX_PAYLOAD + 6u];
-    uint16_t frame_len = 0u;
-    uint16_t remaining;
-    uint16_t chunk_len;
-    uint8_t uart_mask;
-    uart_trans_send_result_t uart_result;
-
-    if (accepted_len == NULL || msg == NULL || offset >= msg->len) {
-        return UART_TRANS_SEND_INVALID_INPUT;
-    }
-
-    *accepted_len = 0u;
-
-    uart_mask = (uint8_t)(msg->dst_mask & (ENDPOINT_UART2 | ENDPOINT_UART3));
-    if ((msg->dst_mask != uart_mask) ||
-        (uart_mask != ENDPOINT_UART2 && uart_mask != ENDPOINT_UART3)) {
-        return UART_TRANS_SEND_INVALID_INPUT;
-    }
-
-    remaining = (uint16_t)(msg->len - offset);
-
-    if (uart_mask == ENDPOINT_UART2) {
-        if (config_get()->mux_mode == MUX_MODE_FRAME) {
-            chunk_len = remaining;
-            if (chunk_len > (uint16_t)(UART_TX_RING_BUFFER_SIZE - 1u - 6u)) {
-                chunk_len = (uint16_t)(UART_TX_RING_BUFFER_SIZE - 1u - 6u);
-            }
-            if (!uart_mux_encode_frame(msg->src_id, ENDPOINT_UART2, &msg->data[offset], chunk_len, frame, &frame_len, sizeof(frame))) {
-                return UART_TRANS_SEND_INVALID_INPUT;
-            }
-            uart_result = uart_trans_send_buffer(UART_CHANNEL_U0, frame, frame_len);
-            if (uart_result != UART_TRANS_SEND_OK) {
-                return uart_result;
-            }
-            *accepted_len = chunk_len;
-            return UART_TRANS_SEND_OK;
-        }
-
-        chunk_len = remaining;
-        if (chunk_len > (uint16_t)(UART_TX_RING_BUFFER_SIZE - 1u)) {
-            chunk_len = (uint16_t)(UART_TX_RING_BUFFER_SIZE - 1u);
-        }
-        uart_result = uart_trans_send_buffer(UART_CHANNEL_U0, &msg->data[offset], chunk_len);
-        if (uart_result != UART_TRANS_SEND_OK) {
-            return uart_result;
-        }
-        *accepted_len = chunk_len;
-        return UART_TRANS_SEND_OK;
-    }
-
-    if (config_get()->mux_mode == MUX_MODE_FRAME) {
-        chunk_len = remaining;
-        if (chunk_len > (uint16_t)(UART_TX_RING_BUFFER_SIZE - 1u - 6u)) {
-            chunk_len = (uint16_t)(UART_TX_RING_BUFFER_SIZE - 1u - 6u);
-        }
-        if (!uart_mux_encode_frame(msg->src_id, ENDPOINT_UART3, &msg->data[offset], chunk_len, frame, &frame_len, sizeof(frame))) {
-            return UART_TRANS_SEND_INVALID_INPUT;
-        }
-        uart_result = uart_trans_send_buffer(UART_CHANNEL_U1, frame, frame_len);
-        if (uart_result != UART_TRANS_SEND_OK) {
-            return uart_result;
-        }
-        *accepted_len = chunk_len;
-        return UART_TRANS_SEND_OK;
-    }
-
-    chunk_len = remaining;
-    if (chunk_len > (uint16_t)(UART_TX_RING_BUFFER_SIZE - 1u)) {
-        chunk_len = (uint16_t)(UART_TX_RING_BUFFER_SIZE - 1u);
-    }
-    uart_result = uart_trans_send_buffer(UART_CHANNEL_U1, &msg->data[offset], chunk_len);
-    if (uart_result != UART_TRANS_SEND_OK) {
-        return uart_result;
-    }
-    *accepted_len = chunk_len;
-    return UART_TRANS_SEND_OK;
-}
-
-static void uart_try_advance_pending_tcp_msg(route_msg_t **pending_tcp_msg,
-                                             uint16_t *pending_tcp_offset,
-                                             uart_trans_send_result_t *pending_tcp_result)
-{
-    route_msg_t *msg;
-    uart_trans_send_result_t uart_result;
-    uint16_t accepted_len;
-
-    if (pending_tcp_msg == NULL || pending_tcp_offset == NULL || pending_tcp_result == NULL) {
-        return;
-    }
-
-    msg = *pending_tcp_msg;
-    if (msg == NULL) {
-        return;
-    }
-
-    for (;;) {
-        accepted_len = 0u;
-        uart_result = uart_send_tcp_msg_chunk(msg, *pending_tcp_offset, &accepted_len);
-        if (uart_result != UART_TRANS_SEND_OK) {
-            if (uart_result != *pending_tcp_result) {
-                debug_log_printf("[UART] tcp-pend src=0x%02X dst=0x%02X off=%u rc=%s\r\n",
-                                 (unsigned int)msg->src_id,
-                                 (unsigned int)msg->dst_mask,
-                                 (unsigned int)(*pending_tcp_offset),
-                                 uart_trans_send_result_to_str(uart_result));
-                *pending_tcp_result = uart_result;
-            }
-            break;
-        }
-
-        *pending_tcp_offset = (uint16_t)(*pending_tcp_offset + accepted_len);
-        *pending_tcp_result = UART_TRANS_SEND_OK;
-        if (*pending_tcp_offset >= msg->len) {
-            route_msg_free(msg);
-            *pending_tcp_msg = NULL;
-            *pending_tcp_offset = 0u;
-            break;
-        }
-    }
-}
-
-static void uart_route_mux_frame(uart_channel_t source_channel, const uart_mux_frame_t *frame)
-{
-    const device_config_t *cfg = config_get();
-    uint32_t i;
-    uint8_t endpoint;
-    uint8_t source_conn = (source_channel == UART_CHANNEL_U1) ? ROUTE_CONN_UART3 : ROUTE_CONN_UART2;
-    uint8_t out_frame[ROUTE_MSG_MAX_PAYLOAD + 6u];
-    uint16_t out_frame_len = 0u;
-    route_send_result_t route_result;
-    uart_trans_send_result_t uart_result;
-
-    if (frame->dst_mask == 0u) {
-        route_result = route_send(xConfigQueue,
-                                  frame->src_id,
-                                  0u,
-                                  source_conn,
-                                  frame->payload,
-                                  frame->payload_len,
-                                  pdMS_TO_TICKS(10));
-        if (route_result != ROUTE_SEND_OK) {
-            debug_log_printf("[UART] mux-cfg-fail rc=%s len=%u\r\n",
-                             route_send_result_to_str(route_result),
-                             (unsigned int)frame->payload_len);
-        }
-        return;
-    }
-
-    for (i = 0; i < CONFIG_LINK_COUNT; ++i) {
-        if (cfg->links[i].enabled == 0u) {
-            continue;
-        }
-        endpoint = config_link_index_to_endpoint((uint8_t)i);
-        if ((frame->dst_mask & endpoint) != 0u) {
-            route_result = route_send(xLinkTxQueues[i], frame->src_id, endpoint, source_conn, frame->payload, frame->payload_len, pdMS_TO_TICKS(10));
-            if (route_result != ROUTE_SEND_OK) {
-                debug_log_printf("[UART] mux-route-fail idx=%u rc=%s len=%u\r\n",
-                                 (unsigned int)i,
-                                 route_send_result_to_str(route_result),
-                                 (unsigned int)frame->payload_len);
-            }
-        }
-    }
-
-    if ((frame->dst_mask & ENDPOINT_UART2) != 0u && source_channel != UART_CHANNEL_U0) {
-        if (uart_mux_encode_frame(frame->src_id, ENDPOINT_UART2, frame->payload, frame->payload_len, out_frame, &out_frame_len, sizeof(out_frame))) {
-            uart_result = uart_trans_send_buffer(UART_CHANNEL_U0, out_frame, out_frame_len);
-            if (uart_result != UART_TRANS_SEND_OK) {
-                debug_log_printf("[UART] mux-u0-tx-fail rc=%s len=%u\r\n",
-                                 uart_trans_send_result_to_str(uart_result),
-                                 (unsigned int)out_frame_len);
-            }
-        } else {
-            debug_log_printf("[UART] mux-u0-enc-fail len=%u\r\n", (unsigned int)frame->payload_len);
-        }
-    }
-
-    if ((frame->dst_mask & ENDPOINT_UART3) != 0u && source_channel != UART_CHANNEL_U1) {
-        if (uart_mux_encode_frame(frame->src_id, ENDPOINT_UART3, frame->payload, frame->payload_len, out_frame, &out_frame_len, sizeof(out_frame))) {
-            uart_result = uart_trans_send_buffer(UART_CHANNEL_U1, out_frame, out_frame_len);
-            if (uart_result != UART_TRANS_SEND_OK) {
-                debug_log_printf("[UART] mux-u1-tx-fail rc=%s len=%u\r\n",
-                                 uart_trans_send_result_to_str(uart_result),
-                                 (unsigned int)out_frame_len);
-            }
-        } else {
-            debug_log_printf("[UART] mux-u1-enc-fail len=%u\r\n", (unsigned int)frame->payload_len);
-        }
     }
 }
 
@@ -401,160 +120,226 @@ int uart_trans_init(void)
     memset(g_channels, 0, sizeof(g_channels));
     g_channels[UART_CHANNEL_U0].huart = &huart2;
     g_channels[UART_CHANNEL_U1].huart = &huart3;
-    debug_log_printf("[UART] init u0=%p u1=%p\r\n", (void *)g_channels[UART_CHANNEL_U0].huart, (void *)g_channels[UART_CHANNEL_U1].huart);
+    g_channels[UART_CHANNEL_U0].config.baudrate = UART_DEFAULT_BAUDRATE;
+    g_channels[UART_CHANNEL_U1].config.baudrate = UART_DEFAULT_BAUDRATE;
+    g_channels[UART_CHANNEL_U0].initialized = true;
+    g_channels[UART_CHANNEL_U1].initialized = true;
     return 0;
 }
 
-int uart_trans_start_all(void)
+int uart_trans_config(uart_channel_t channel, const uart_config_t *config)
 {
-    uint32_t i;
+    if (channel >= UART_CHANNEL_MAX || config == NULL) {
-    for (i = 0; i < UART_CHANNEL_MAX; ++i) {
-        if (g_channels[i].huart == NULL) {
-            debug_log_printf("[UART] start fail null handle ch=%lu\r\n", (unsigned long)i);
         return -1;
     }
-        g_channels[i].rx_dma_read_index = 0u;
+    g_channels[channel].config = *config;
-        g_channels[i].rx_head = 0u;
+    return apply_uart_config(channel);
-        g_channels[i].rx_tail = 0u;
-        g_channels[i].tx_head = 0u;
-        g_channels[i].tx_tail = 0u;
-        g_channels[i].tx_dma_len = 0u;
-        g_channels[i].tx_busy = 0u;
-        __HAL_UART_ENABLE_IT(g_channels[i].huart, UART_IT_IDLE);
-        if (HAL_UART_Receive_DMA(g_channels[i].huart, g_channels[i].rx_dma_buffer, UART_RX_DMA_BUFFER_SIZE) != HAL_OK) {
-            debug_log_printf("[UART] dma start fail ch=%lu\r\n", (unsigned long)i);
-            return -1;
-        }
-    }
-    debug_log_write("[UART] rx dma started\r\n");
-    return 0;
 }
 
-uart_trans_send_result_t uart_trans_send_buffer(uart_channel_t channel, const uint8_t *data, uint16_t len)
+int uart_trans_start(uart_channel_t channel)
 {
     uart_channel_ctx_t *ctx;
-    uart_trans_send_result_t uart_result;
-    uint16_t original_head;
-    uint16_t written = 0u;
 
-    if (channel >= UART_CHANNEL_MAX || data == NULL || len == 0u || len >= UART_TX_RING_BUFFER_SIZE) {
+    if (channel >= UART_CHANNEL_MAX) {
-        return UART_TRANS_SEND_INVALID_INPUT;
+        return -1;
     }
 
     ctx = &g_channels[channel];
-    if (ctx->huart == NULL) {
+    if (!ctx->initialized || ctx->huart == NULL) {
-        return UART_TRANS_SEND_INVALID_INPUT;
+        return -1;
     }
 
-    taskENTER_CRITICAL();
+    ctx->rx_dma_read_index = 0u;
-    original_head = ctx->tx_head;
+    ctx->rx_head = 0u;
-    if (ring_free(ctx->tx_head, ctx->tx_tail, UART_TX_RING_BUFFER_SIZE) < len) {
+    ctx->rx_tail = 0u;
-        taskEXIT_CRITICAL();
+    ctx->tx_head = 0u;
-        return UART_TRANS_SEND_RING_FULL;
+    ctx->tx_tail = 0u;
+    ctx->tx_dma_len = 0u;
+    ctx->tx_busy = false;
+    memset(&ctx->stats, 0, sizeof(ctx->stats));
+
+    __HAL_UART_ENABLE_IT(ctx->huart, UART_IT_IDLE);
+    if (HAL_UART_Receive_DMA(ctx->huart, ctx->rx_dma_buffer, UART_RX_DMA_BUFFER_SIZE) != HAL_OK) {
+        return -1;
     }
 
-    while (written < len) {
+    ctx->running = true;
+    return 0;
+}
+
+int uart_trans_stop(uart_channel_t channel)
+{
+    if (channel >= UART_CHANNEL_MAX) {
+        return -1;
+    }
+    HAL_UART_DMAStop(g_channels[channel].huart);
+    g_channels[channel].running = false;
+    g_channels[channel].tx_busy = false;
+    return 0;
+}
+
+void uart_trans_poll(void)
+{
+    kick_tx(UART_CHANNEL_U0);
+    kick_tx(UART_CHANNEL_U1);
+}
+
+uint16_t uart_trans_rx_available(uart_channel_t channel)
+{
+    if (channel >= UART_CHANNEL_MAX) {
+        return 0u;
+    }
+    return ring_used(g_channels[channel].rx_head, g_channels[channel].rx_tail, UART_RX_RING_BUFFER_SIZE);
+}
+
+uint16_t uart_trans_read(uart_channel_t channel, uint8_t *data, uint16_t max_len)
+{
+    uart_channel_ctx_t *ctx;
+    uint16_t copied = 0u;
+
+    if (channel >= UART_CHANNEL_MAX || data == NULL || max_len == 0u) {
+        return 0u;
+    }
+
+    ctx = &g_channels[channel];
+    while (copied < max_len && ctx->rx_tail != ctx->rx_head) {
+        data[copied++] = ctx->rx_ring[ctx->rx_tail];
+        ctx->rx_tail = (uint16_t)((ctx->rx_tail + 1u) % UART_RX_RING_BUFFER_SIZE);
+    }
+    if (copied > 0u) {
+        ctx->stats.rx_packets++;
+    }
+    return copied;
+}
+
+uint16_t uart_trans_write(uart_channel_t channel, const uint8_t *data, uint16_t len)
+{
+    uart_channel_ctx_t *ctx;
+    uint16_t written = 0u;
+
+    if (channel >= UART_CHANNEL_MAX || data == NULL || len == 0u) {
+        return 0u;
+    }
+
+    ctx = &g_channels[channel];
+    while (written < len && ring_free(ctx->tx_head, ctx->tx_tail, UART_TX_RING_BUFFER_SIZE) > 0u) {
         ctx->tx_ring[ctx->tx_head] = data[written++];
         ctx->tx_head = (uint16_t)((ctx->tx_head + 1u) % UART_TX_RING_BUFFER_SIZE);
     }
 
-    uart_result = kick_tx(channel);
+    if (written < len) {
-    if (uart_result != UART_TRANS_SEND_OK) {
+        ctx->stats.errors++;
-        ctx->tx_head = original_head;
-        taskEXIT_CRITICAL();
-        return uart_result;
     }
 
-    taskEXIT_CRITICAL();
+    kick_tx(channel);
-
+    return written;
-    return UART_TRANS_SEND_OK;
 }
 
-void uart_trans_notify_rx_from_isr(uart_channel_t channel, BaseType_t *xHigherPriorityTaskWoken)
+void uart_trans_get_stats(uart_channel_t channel, uart_stats_t *stats)
 {
-    uint32_t notify = (channel == UART_CHANNEL_U1) ? UART_NOTIFY_RX_U1 : UART_NOTIFY_RX_U0;
+    if (channel < UART_CHANNEL_MAX && stats != NULL) {
-    if (xUartRxTaskHandle != NULL) {
+        *stats = g_channels[channel].stats;
-        xTaskNotifyFromISR(xUartRxTaskHandle, notify, eSetBits, xHigherPriorityTaskWoken);
     }
 }
 
+void uart_trans_reset_stats(uart_channel_t channel)
+{
+    if (channel < UART_CHANNEL_MAX) {
+        memset(&g_channels[channel].stats, 0, sizeof(g_channels[channel].stats));
+    }
+}
+
+void uart_trans_idle_handler(uart_channel_t channel)
+{
+    UART_HandleTypeDef *huart;
+    uint16_t dma_write_index;
+
+    if (channel >= UART_CHANNEL_MAX) {
+        return;
+    }
+    huart = g_channels[channel].huart;
+    g_channels[channel].stats.idle_events++;
+    dma_write_index = (uint16_t)(UART_RX_DMA_BUFFER_SIZE - __HAL_DMA_GET_COUNTER(huart->hdmarx));
+    if (dma_write_index >= UART_RX_DMA_BUFFER_SIZE) {
+        dma_write_index = 0u;
+    }
+    process_rx_snapshot(channel, dma_write_index);
+}
+
+void uart_trans_rx_half_cplt_handler(uart_channel_t channel)
+{
+    if (channel >= UART_CHANNEL_MAX) {
+        return;
+    }
+    g_channels[channel].stats.rx_half_events++;
+    process_rx_snapshot(channel, UART_RX_DMA_BUFFER_SIZE / 2u);
+}
+
+void uart_trans_rx_cplt_handler(uart_channel_t channel)
+{
+    if (channel >= UART_CHANNEL_MAX) {
+        return;
+    }
+    g_channels[channel].stats.rx_full_events++;
+    process_rx_snapshot(channel, 0u);
+}
+
 void uart_trans_tx_cplt_handler(uart_channel_t channel)
 {
-    uint32_t notify = (channel == UART_CHANNEL_U1) ? UART_NOTIFY_TX_U1 : UART_NOTIFY_TX_U0;
+    if (channel >= UART_CHANNEL_MAX) {
-    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+        return;
-    if (xUartRxTaskHandle != NULL) {
-        xTaskNotifyFromISR(xUartRxTaskHandle, notify, eSetBits, &xHigherPriorityTaskWoken);
-        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
     }
+    g_channels[channel].tx_busy = false;
+    g_channels[channel].stats.tx_bytes += g_channels[channel].tx_dma_len;
+    g_channels[channel].tx_dma_len = 0u;
+    kick_tx(channel);
 }
 
 bool uart_mux_try_extract_frame(uart_channel_t channel, uart_mux_frame_t *frame)
 {
+    uint8_t header[5];
     uint16_t available;
     uint16_t payload_len;
-    uint8_t sync_byte;
-    uint16_t i;
 
-    if (frame == NULL) {
+    if (channel >= UART_CHANNEL_MAX || frame == NULL) {
-        return false;
-    }
-
-    available = uart_ring_available(channel);
-    if (available == 0u) {
-        return false;
-    }
-
-    if (!uart_ring_peek_byte(channel, 0u, &sync_byte)) {
-        return false;
-    }
-
-    if (sync_byte != UART_MUX_SYNC) {
-        uart_ring_drop(channel, 1u);
         return false;
     }
 
+    available = uart_trans_rx_available(channel);
     if (available < 6u) {
         return false;
     }
 
-    if (!uart_ring_peek_byte(channel, 1u, &sync_byte)) {
+    if (uart_trans_read(channel, header, sizeof(header)) != sizeof(header)) {
         return false;
     }
-    payload_len = (uint16_t)((uint16_t)sync_byte << 8);
+    if (header[0] != UART_MUX_SYNC) {
-    if (!uart_ring_peek_byte(channel, 2u, &sync_byte)) {
         return false;
     }
-    payload_len = (uint16_t)(payload_len | sync_byte);
+
+    payload_len = (uint16_t)(((uint16_t)header[1] << 8) | header[2]);
     if (payload_len > sizeof(frame->payload)) {
-        uart_ring_drop(channel, 1u);
+        return false;
-        return false;
+    }
-    }
+    if (uart_trans_rx_available(channel) < (uint16_t)(payload_len + 1u)) {
-
-    if (available < (uint16_t)(payload_len + 6u)) {
-        return false;
-    }
-
-    if (!uart_ring_peek_byte(channel, 5u + payload_len, &sync_byte)) {
-        return false;
-    }
-    if (sync_byte != UART_MUX_TAIL) {
-        uart_ring_drop(channel, 1u);
-        return false;
-    }
-
-    if (!uart_ring_peek_byte(channel, 3u, &frame->src_id) ||
-        !uart_ring_peek_byte(channel, 4u, &frame->dst_mask)) {
         return false;
     }
 
+    frame->src_id = header[3];
+    frame->dst_mask = header[4];
     frame->payload_len = payload_len;
-    for (i = 0u; i < payload_len; ++i) {
+    if (payload_len > 0u) {
-        if (!uart_ring_peek_byte(channel, (uint16_t)(5u + i), &frame->payload[i])) {
+        if (uart_trans_read(channel, frame->payload, payload_len) != payload_len) {
             return false;
         }
     }
 
-    uart_ring_drop(channel, (uint16_t)(payload_len + 6u));
+    {
+        uint8_t tail = 0u;
+        if (uart_trans_read(channel, &tail, 1u) != 1u || tail != UART_MUX_TAIL) {
+            return false;
+        }
+    }
 
     return true;
 }
@@ -567,9 +352,13 @@ bool uart_mux_encode_frame(uint8_t src_id,
                            uint16_t *out_len,
                            uint16_t out_capacity)
 {
-    uint16_t frame_len = (uint16_t)(payload_len + 6u);
+    uint16_t frame_len;
 
-    if (out == NULL || out_len == NULL || frame_len > out_capacity) {
+    if (out == NULL || out_len == NULL) {
+        return false;
+    }
+    frame_len = (uint16_t)(payload_len + 6u);
+    if (frame_len > out_capacity) {
         return false;
     }
 
@@ -585,65 +374,3 @@ bool uart_mux_encode_frame(uint8_t src_id,
     *out_len = frame_len;
     return true;
 }
-
-void UartRxTask(void *argument)
-{
-    uint32_t notify_value;
-    BaseType_t notified;
-    route_msg_t *msg;
-    route_msg_t *pending_tcp_msg = NULL;
-    uint16_t pending_tcp_offset = 0u;
-    uart_mux_frame_t frame;
-    const device_config_t *cfg;
-    uart_trans_send_result_t pending_tcp_result = UART_TRANS_SEND_OK;
-
-    (void)argument;
-    if (uart_trans_start_all() != 0) {
-        Debug_TrapWithRttHint("uart-start-fail");
-        vTaskSuspend(NULL);
-    }
-    debug_log_boot("uart-task-started");
-
-    for (;;) {
-        notify_value = 0u;
-        notified = xTaskNotifyWait(0u, 0xFFFFFFFFu, &notify_value, pdMS_TO_TICKS(10));
-
-        if ((notified == pdTRUE) && ((notify_value & UART_NOTIFY_RX_U0) != 0u)) {
-            process_rx_snapshot(UART_CHANNEL_U0);
-        }
-        if ((notified == pdTRUE) && ((notify_value & UART_NOTIFY_RX_U1) != 0u)) {
-            process_rx_snapshot(UART_CHANNEL_U1);
-        }
-        if ((notified == pdTRUE) && ((notify_value & UART_NOTIFY_TX_U0) != 0u)) {
-            g_channels[UART_CHANNEL_U0].tx_busy = 0u;
-        }
-        if ((notified == pdTRUE) && ((notify_value & UART_NOTIFY_TX_U1) != 0u)) {
-            g_channels[UART_CHANNEL_U1].tx_busy = 0u;
-        }
-
-        uart_try_advance_pending_tcp_msg(&pending_tcp_msg, &pending_tcp_offset, &pending_tcp_result);
-
-        while (pending_tcp_msg == NULL && xQueueReceive(xTcpRxQueue, &msg, 0) == pdPASS) {
-            pending_tcp_msg = msg;
-            pending_tcp_offset = 0u;
-            pending_tcp_result = UART_TRANS_SEND_OK;
-            uart_try_advance_pending_tcp_msg(&pending_tcp_msg, &pending_tcp_offset, &pending_tcp_result);
-        }
-
-        cfg = config_get();
-        if (cfg->mux_mode == MUX_MODE_FRAME) {
-            while (uart_mux_try_extract_frame(UART_CHANNEL_U0, &frame)) {
-                uart_route_mux_frame(UART_CHANNEL_U0, &frame);
-            }
-            while (uart_mux_try_extract_frame(UART_CHANNEL_U1, &frame)) {
-                uart_route_mux_frame(UART_CHANNEL_U1, &frame);
-            }
-        } else {
-            uart_route_raw_channel(UART_CHANNEL_U0);
-            uart_route_raw_channel(UART_CHANNEL_U1);
-        }
-
-        kick_tx(UART_CHANNEL_U0);
-        kick_tx(UART_CHANNEL_U1);
-    }
-}

App/uart_trans.h

@@ -1,11 +1,14 @@
-#ifndef UART_TRANS_H
+/**
-#define UART_TRANS_H
+ * @file uart_trans.h
+ * @brief Bare-metal UART DMA/IDLE transport and MUX framing helpers.
+ */
+
+#ifndef __UART_TRANS_H__
+#define __UART_TRANS_H__
 
 #include <stdbool.h>
 #include <stdint.h>
 
-#include "FreeRTOS.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -16,13 +19,6 @@ typedef enum {
     UART_CHANNEL_MAX
 } uart_channel_t;
 
-typedef enum {
-    UART_TRANS_SEND_OK = 0,
-    UART_TRANS_SEND_INVALID_INPUT,
-    UART_TRANS_SEND_RING_FULL,
-    UART_TRANS_SEND_KICK_FAILED
-} uart_trans_send_result_t;
-
 typedef struct {
     uint8_t src_id;
     uint8_t dst_mask;
@@ -30,18 +26,41 @@ typedef struct {
     uint8_t payload[256];
 } uart_mux_frame_t;
 
-#define UART_RX_DMA_BUFFER_SIZE   128u
+#define UART_RX_DMA_BUFFER_SIZE   256u
-#define UART_TX_DMA_BUFFER_SIZE   128u
+#define UART_TX_DMA_BUFFER_SIZE   256u
-#define UART_RX_RING_BUFFER_SIZE  256u
+#define UART_RX_RING_BUFFER_SIZE  512u
-#define UART_TX_RING_BUFFER_SIZE  256u
+#define UART_TX_RING_BUFFER_SIZE  384u
+#define UART_DEFAULT_BAUDRATE     115200u
+
+typedef struct {
+    uint32_t baudrate;
+} uart_config_t;
+
+typedef struct {
+    uint32_t rx_bytes;
+    uint32_t tx_bytes;
+    uint32_t rx_packets;
+    uint32_t tx_packets;
+    uint32_t idle_events;
+    uint32_t rx_half_events;
+    uint32_t rx_full_events;
+    uint32_t errors;
+} uart_stats_t;
 
 int uart_trans_init(void);
-int uart_trans_start_all(void);
+int uart_trans_config(uart_channel_t channel, const uart_config_t *config);
-const char *uart_trans_send_result_to_str(uart_trans_send_result_t result);
+int uart_trans_start(uart_channel_t channel);
-uart_trans_send_result_t uart_trans_send_buffer(uart_channel_t channel, const uint8_t *data, uint16_t len);
+int uart_trans_stop(uart_channel_t channel);
-void uart_trans_notify_rx_from_isr(uart_channel_t channel, BaseType_t *xHigherPriorityTaskWoken);
+void uart_trans_poll(void);
+uint16_t uart_trans_rx_available(uart_channel_t channel);
+uint16_t uart_trans_read(uart_channel_t channel, uint8_t *data, uint16_t max_len);
+uint16_t uart_trans_write(uart_channel_t channel, const uint8_t *data, uint16_t len);
+void uart_trans_get_stats(uart_channel_t channel, uart_stats_t *stats);
+void uart_trans_reset_stats(uart_channel_t channel);
+void uart_trans_idle_handler(uart_channel_t channel);
+void uart_trans_rx_half_cplt_handler(uart_channel_t channel);
+void uart_trans_rx_cplt_handler(uart_channel_t channel);
 void uart_trans_tx_cplt_handler(uart_channel_t channel);
-void UartRxTask(void *argument);
 bool uart_mux_try_extract_frame(uart_channel_t channel, uart_mux_frame_t *frame);
 bool uart_mux_encode_frame(uint8_t src_id,
                            uint8_t dst_mask,
@@ -55,4 +74,4 @@ bool uart_mux_encode_frame(uint8_t src_id,
 }
 #endif
 
-#endif
+#endif /* __UART_TRANS_H__ */

CH390_RX_PBUF泄漏修复复盘.md

@@ -1,245 +0,0 @@
-# CH390 / lwIP 固定次数 ping 失败问题修复复盘
-
-## 1. 问题现象
-
-在 TCP2UART 固件运行后，设备初期可以正常 ARP 和 ping，但连续 ping 一段时间后不再响应。
-
-典型现象：
-
-- 设备 IP：`192.168.31.100`
-- 设备 MAC：`02:00:00:00:00:01`
-- 对端/网关 IP：`192.168.31.1`
-- 对端/网关 MAC：`00:e0:4c:28:1e:60`
-- 失败后设备仍持续发送 TCP SYN/RST 或 client timeout 相关流量，说明 TX、任务调度和应用层并未整体死机。
-- 失败后对端继续向设备 MAC 发送 ICMP/ARP，但设备不再回复。
-
-关键抓包：
-
-- `WiresharkLog/04290150.pcapng`
-  - `seq=1884..1891` 共 8 次 ping reply 正常。
-  - 第 9 次 `seq=1892` 开始无 reply。
-- `WiresharkLog/04290206.pcapng`
-  - 曾把 `PBUF_POOL_SIZE` / `MEMP_NUM_TCPIP_MSG_INPKT` 从 8 临时扩大到 16。
-  - 成功 ping 从 8 次变为 `seq=1900..1915` 共 16 次。
-  - 第 17 次 `seq=1916` 开始无 reply。
-
-这个“成功次数随池大小移动”的现象证明：问题不是 CH390 随机丢包，也不是 PHY/TX 死掉，而是每次成功处理 ping 后都有某个 pbuf 引用没有释放，最终耗尽 `PBUF_POOL`。
-
-## 2. 排查过程中的重要结论
-
-### 2.1 CH390 RX 读包路径曾存在风险，但不是最终根因
-
-早期排查时发现 CH390 RX 路径与参考驱动存在若干不一致，已修正：
-
-- `ch390_receive_packet()` 按参考序列读取 RX ready：先读 `MRCMDX` dummy，再读 `MRCMDX1`。
-- 校验 RX header 的 `Head` 字节必须为 `CH390_PKT_RDY`。
-- CH390 RX SRAM 中的 `rx_len` 包含 Ethernet FCS，交给 lwIP 前需要减去 4 字节。
-- `ch390_rx_reset()` 显式写 `MPTRCR_RST_RX` 复位 RX memory pointer。
-
-这些修正确保 CH390 RX FIFO 读包更接近参考实现，但无法解释“固定 8 次/16 次后失败”。
-
-### 2.2 扩大 lwIP 池只能延迟问题
-
-曾临时将如下配置从 8 提到 16：
-
-```c
-#define PBUF_POOL_SIZE           16
-#define MEMP_NUM_PBUF            16
-#define MEMP_NUM_TCPIP_MSG_INPKT 16
-```
-
-结果成功 ping 次数也从 8 变成 16。这说明扩大池子只是延迟耗尽，不能作为根修复。
-
-最终已恢复为 8：
-
-```c
-#define PBUF_POOL_SIZE           8
-#define MEMP_NUM_PBUF            8
-#define MEMP_NUM_TCPIP_MSG_INPKT 8
-```
-
-### 2.3 `tcpip_input()` 异步队列不是最终根因
-
-项目启用了 lwIP core locking。为避免每个 RX 包占用 `MEMP_TCPIP_MSG_INPKT`，配置已改为同步输入：
-
-```c
-#define LWIP_TCPIP_CORE_LOCKING       1
-#define LWIP_TCPIP_CORE_LOCKING_INPUT 1
-```
-
-这样 `tcpip_input()` 会在 core lock 下同步调用 `ethernet_input()`，不再通过 `TCPIP_MSG_INPKT` 邮箱异步排队。
-
-但用户后续验证仍然固定 8 次后停止，且每次成功 ping 都已经有 reply，因此说明 RX 包确实已经进入 ICMP 处理路径，问题更可能是 reply 输出路径增加了 pbuf 引用但未释放。
-
-## 3. 最终根因
-
-最终根因位于：
-
-```text
-Drivers/LwIP/src/netif/ethernet.c
-```
-
-原 `ethernet_output()` 实现：
-
-```c
-q = pbuf_alloc(PBUF_RAW_TX, SIZEOF_ETH_HDR, PBUF_RAM);
-if (q == NULL) {
-  LINK_STATS_INC(link.memerr);
-  LINK_STATS_INC(link.drop);
-  return ERR_MEM;
-}
-
-pbuf_chain(q, p);
-
-ethhdr = (struct eth_hdr *)q->payload;
-SMEMCPY(&ethhdr->dest, dst, sizeof(struct eth_addr));
-SMEMCPY(&ethhdr->src, src, sizeof(struct eth_addr));
-ethhdr->type = lwip_htons(eth_type);
-
-return netif->linkoutput(netif, q);
-```
-
-问题在 `pbuf_chain(q, p)`。
-
-lwIP 的 `pbuf_chain()` 会执行：
-
-```c
-pbuf_ref(t);
-```
-
-也就是给被挂接的原始 pbuf `p` 引用计数加 1。
-
-ICMP echo reply 路径会复用 RX pbuf：
-
-```text
-ethernetif_poll()
-  -> tcpip_input()
-  -> ethernet_input()
-  -> ip4_input()
-  -> icmp_input()
-  -> ip4_output_if()
-  -> etharp_output()
-  -> ethernet_output()
-```
-
-`icmp_input()` 末尾本身会 `pbuf_free(p)`，这部分是正确的。但在原实现中，`ethernet_output()` 通过 `pbuf_chain(q, p)` 给 `p` 额外加了一次引用，却没有在 `linkoutput()` 返回后释放临时 header pbuf `q`。
-
-因此每次 ping 的引用计数变化是：
-
-```text
-RX pbuf 初始 ref = 1
-pbuf_chain(q, p) 后 ref = 2
-icmp_input() 末尾 pbuf_free(p) 后 ref = 1
-=> p 永远没有回到 0，PBUF_POOL 泄漏 1 个
-```
-
-所以：
-
-- `PBUF_POOL_SIZE=8` 时，8 次 ping reply 后耗尽。
-- 临时扩大到 16 时，16 次 ping reply 后耗尽。
-
-## 4. 修复方案
-
-修复 `ethernet_output()`，在同步 `linkoutput()` 完成后释放临时 header pbuf 链：
-
-```c
-err_t ethernet_output(struct netif *netif,
-                      struct pbuf *p,
-                      const struct eth_addr *src,
-                      const struct eth_addr *dst,
-                      u16_t eth_type)
-{
-  struct pbuf *q;
-  struct eth_hdr *ethhdr;
-  err_t err;
-
-  LWIP_ASSERT("netif != NULL", netif != NULL);
-  LWIP_ASSERT("p != NULL", p != NULL);
-  LWIP_ASSERT("src != NULL", src != NULL);
-  LWIP_ASSERT("dst != NULL", dst != NULL);
-
-  q = pbuf_alloc(PBUF_RAW_TX, SIZEOF_ETH_HDR, PBUF_RAM);
-  if (q == NULL) {
-    LINK_STATS_INC(link.memerr);
-    LINK_STATS_INC(link.drop);
-    return ERR_MEM;
-  }
-
-  pbuf_chain(q, p);
-
-  ethhdr = (struct eth_hdr *)q->payload;
-  SMEMCPY(&ethhdr->dest, dst, sizeof(struct eth_addr));
-  SMEMCPY(&ethhdr->src, src, sizeof(struct eth_addr));
-  ethhdr->type = lwip_htons(eth_type);
-
-  err = netif->linkoutput(netif, q);
-  pbuf_free(q);
-  return err;
-}
-```
-
-为什么这里可以释放 `q`：
-
-- 本项目 `low_level_output()` 是同步发送。
-- 它会立即遍历 pbuf 链，把数据复制到 `s_tx_buffer`。
-- 随后调用 `ch390_runtime_send_packet()` 把连续 buffer 发给 CH390。
-- `low_level_output()` 返回后不再持有 pbuf 指针。
-
-因此 `ethernet_output()` 在 `linkoutput()` 返回后释放 `q` 是正确的。
-
-`pbuf_free(q)` 会同时：
-
-- 释放临时 Ethernet header pbuf `q`；
-- 解除 `pbuf_chain()` 对原始 RX pbuf `p` 增加的引用；
-- 之后 `icmp_input()` 末尾的 `pbuf_free(p)` 可以真正把 RX pbuf 归还 `PBUF_POOL`。
-
-## 5. 不要做的错误修复
-
-### 5.1 不要在 `netif->input()` 成功后手动释放 pbuf
-
-驱动层当前逻辑是正确的：
-
-```c
-input_err = ch390_netif.input(p, &ch390_netif);
-if (input_err != ERR_OK) {
-    pbuf_free(p);
-}
-```
-
-`netif->input()` 返回 `ERR_OK` 时，pbuf ownership 已经交给 lwIP。此时驱动不能再 `pbuf_free(p)`，否则会造成 double-free 或 use-after-free。
-
-### 5.2 不要只扩大 `PBUF_POOL_SIZE`
-
-扩大池子只会让失败次数从 8 变 16、32……不会修复泄漏。
-
-### 5.3 不要继续优先怀疑 CH390 PHY/TX
-
-抓包中失败后设备仍持续发送 TCP SYN/RST，说明 TX 和任务仍活着。固定次数失败更符合 pbuf 引用泄漏。
-
-## 6. 验证结果
-
-修复后 Keil 构建通过：
-
-```text
-"TCP2UART\TCP2UART.axf" - 0 Error(s), 0 Warning(s).
-Program Size: Code=93376 RO-data=2768 RW-data=456 ZI-data=56032
-```
-
-用户烧录验证后确认问题已修复。
-
-## 7. 后续排查建议
-
-如后续再次出现固定次数网络停止，优先检查：
-
-1. 是否存在 `pbuf_chain()` / `pbuf_ref()` 后没有配对 `pbuf_free()` 的路径。
-2. 是否有 ARP pending queue 长时间持有 pbuf。
-3. 是否有 TCP `recvmbox` / 应用桥接队列背压长期持有 pbuf。
-4. 是否有人在 `netif->input()` 成功后错误释放 pbuf，导致内存破坏。
-
-推荐排查点：
-
-- `Drivers/LwIP/src/netif/ethernet.c`
-- `Drivers/LwIP/src/core/ipv4/icmp.c`
-- `Drivers/LwIP/src/core/ipv4/etharp.c`
-- `Drivers/LwIP/src/core/pbuf.c`
-- `Drivers/LwIP/src/netif/ethernetif.c`

CH390_最终结论报告.md

@@ -0,0 +1,105 @@
+# CH390 最终结论报告
+
+## 结论
+
+本轮循环调试的最终结论是：
+
+1. 当前工程中的主要软件问题已经完成收敛和清理。
+2. CH390D 驱动、lwIP `netif`、ARP 与 ICMP 基本链路已经在实机上打通。
+3. 本轮最终根因已确认不是普通软件逻辑错误，而是 CH390D 相关供电滤波电容虚焊，导致供电不稳定。
+
+## 已完成的软件侧工作
+
+本轮已完成并验证的事项包括：
+
+1. 修复 PHY 访问无超时导致的永久卡死风险。
+2. 修复未初始化 IWDG 句柄刷新导致的 HardFault。
+3. 清理 CH390 运行时中断屏蔽范围，消除阻塞式 SPI 访问造成的运行时假死。
+4. 重构 CH390 运行时所有权，避免多层并发触达底层 SPI 路径。
+5. 在 `main()` 中移除重复 CH390 复位，避免启动阶段额外复位噪声。
+6. 清理已确认 warning 来源，避免无效变量继续污染构建结果。
+7. 增加 CH390 identity gate，避免在无效寄存器读回前继续执行默认配置和 PHY 初始化。
+8. 曾增加 bit-bang 诊断读用于快速隔离问题，该临时调试路径已在当前代码中移除。
+
+## 实机关键证据
+
+### 1. MCU 自身正常工作
+
+已验证：
+
+1. RTT 正常输出。
+2. 主循环正常运行。
+3. `TIM4` 心跳正常。
+4. 运行期不再出现此前已修复的 HardFault 和“长时间假死”症状。
+
+### 2. 最终硬件根因已定位
+
+最终实板排查结果：
+
+1. 板载一颗 CH390D 供电相关滤波电容存在虚焊。
+2. 该问题导致 CH390D 供电不稳定，表现为寄存器读写、链路状态和报文收发在调试过程中不一致。
+3. 修复硬件后，实机已观察到：
+   - `VID=0x1C00`、`PID=0x9151`、`REV=0x2B`
+   - PHY 寄存器稳定可读
+   - `lwIP netif` 能进入 `LINK_UP`
+   - 设备可接收 ARP request 并发出 ARP reply
+   - 设备可接收 ICMP Echo Request 并发出 Echo Reply
+
+### 3. 历史 bit-bang 对照结果（已归档）
+
+在早期调试中，曾绕过 STM32 硬件 SPI 外设、直接用 GPIO 软件时序读取 `VIDL/VIDH/PIDL/PIDH/CHIPR`，RTT 输出为：
+
+```text
+CH390 bitbang VIDL=0xFF VIDH=0xFF PIDL=0xFF PIDH=0xFF CHIPR=0xFF
+```
+
+该历史证据用于定位阶段，当前仅保留结论，不再保留对应代码路径。它说明：
+
+1. 在硬件未修复前，单看软件现象会误导排查方向。
+2. 电源完整性问题会放大为看似“SPI/IRQ/RX/TX 都可疑”的复合症状。
+
+## 外部参考对结论的支撑
+
+对公开 CH390 / DM9051 实现的对照结果表明：
+
+1. CH390 SPI 访问时序、模式选择和 RX SRAM 连续事务仍然值得严格对照参考实现。
+2. 但本项目最终问题并非“参考实现缺失”，而是硬件供电缺陷放大了调试噪声。
+3. 外部参考对软件排查有帮助，但不能替代板级供电与焊接检查。
+
+## 当前最可信判断
+
+最终确认的板级问题为：
+
+1. CH390D 供电滤波电容虚焊。
+2. 该虚焊导致供电稳定性不足，从而引出不稳定的寄存器读写、链路与收发行为。
+
+## 版本库状态
+
+本轮已创建一个阶段性 checkpoint commit：
+
+1. `1808f99` `fix: harden CH390 bring-up diagnostics`
+
+该提交记录了：
+
+1. warning 清理
+2. 移除重复复位
+3. CH390 早期 identity gate
+4. 链路变化稳定等待
+
+## 推荐的下一步
+
+后续更高价值的工作不再是继续怀疑 CH390 是否“完全不通”，而是：
+
+1. 在硬件问题修复后补充长时间稳定性测试。
+2. 验证 TCP Server / TCP Client 业务流量与桥接逻辑在修复硬件后的行为。
+3. 保持驱动层日志最小化，仅在重新排障时按需开启详细 RTT。
+
+## 收尾说明
+
+本轮循环的退出条件已经满足：软件主路径已验证，且硬件根因已定位。
+
+因此当前最合理的结论是：
+
+1. CH390D 驱动、lwIP `netif`、ARP 和 ICMP 基本链路已在实机打通。
+2. 本轮真正拦路的不是普通软件逻辑，而是板级供电滤波电容虚焊。
+3. 后续应在硬件修复后的稳定板卡上继续推进应用层联调与文档收口。

CMakeLists.txt

@@ -0,0 +1,68 @@
+cmake_minimum_required(VERSION 3.22)
+
+#
+# This file is generated only once,
+# and is not re-generated if converter is called multiple times.
+#
+# User is free to modify the file as much as necessary
+#
+
+# Setup compiler settings
+set(CMAKE_C_STANDARD 11)
+set(CMAKE_C_STANDARD_REQUIRED ON)
+set(CMAKE_C_EXTENSIONS ON)
+
+
+# Define the build type
+if(NOT CMAKE_BUILD_TYPE)
+    set(CMAKE_BUILD_TYPE "Debug")
+endif()
+
+# Set the project name
+set(CMAKE_PROJECT_NAME TCP2UART)
+
+# Enable compile command to ease indexing with e.g. clangd
+set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE)
+
+# Core project settings
+project(${CMAKE_PROJECT_NAME})
+message("Build type: " ${CMAKE_BUILD_TYPE})
+
+# Enable CMake support for ASM and C languages
+enable_language(C ASM)
+
+# Create an executable object type
+add_executable(${CMAKE_PROJECT_NAME})
+
+# Add STM32CubeMX generated sources
+add_subdirectory(cmake/stm32cubemx)
+
+# Link directories setup
+target_link_directories(${CMAKE_PROJECT_NAME} PRIVATE
+    # Add user defined library search paths
+)
+
+# Add sources to executable
+target_sources(${CMAKE_PROJECT_NAME} PRIVATE
+    # Add user sources here
+)
+
+# Add include paths
+target_include_directories(${CMAKE_PROJECT_NAME} PRIVATE
+    # Add user defined include paths
+)
+
+# Add project symbols (macros)
+target_compile_definitions(${CMAKE_PROJECT_NAME} PRIVATE
+    # Add user defined symbols
+)
+
+# Remove wrong libob.a library dependency when using cpp files
+list(REMOVE_ITEM CMAKE_C_IMPLICIT_LINK_LIBRARIES ob)
+
+# Add linked libraries
+target_link_libraries(${CMAKE_PROJECT_NAME}
+    stm32cubemx
+
+    # Add user defined libraries
+)

CMakePresets.json

@@ -0,0 +1,38 @@
+{
+    "version": 3,
+    "configurePresets": [
+        {
+            "name": "default",
+            "hidden": true,
+            "generator": "Ninja",
+            "binaryDir": "${sourceDir}/build/${presetName}",
+		    "toolchainFile": "${sourceDir}/cmake/gcc-arm-none-eabi.cmake",
+            "cacheVariables": {
+            }
+        },
+        {
+            "name": "Debug",
+            "inherits": "default",
+            "cacheVariables": {
+                "CMAKE_BUILD_TYPE": "Debug"
+            }
+        },
+        {
+            "name": "Release",
+            "inherits": "default",
+            "cacheVariables": {
+                "CMAKE_BUILD_TYPE": "Release"
+            }
+        }
+    ],
+    "buildPresets": [
+        {
+            "name": "Debug",
+            "configurePreset": "Debug"
+        },
+        {
+            "name": "Release",
+            "configurePreset": "Release"
+        }
+    ]
+}

CODING_PROMPT.md

@@ -1,66 +0,0 @@
-# TCP2UART 当前交接 Prompt
-
-## 1. 用途
-
-本文件不再承担“项目从零编码任务说明”的职责，而是作为**当前工程的交接入口 Prompt**使用。
-
-长期有效的工程知识、调试经验和现状说明，已经分别固化到其它文档，不再全部堆在本文件中。
-
----
-
-## 2. 接手后先读什么
-
-请按以下顺序阅读：
-
-1. `交接清单.md` —— 当前状态、接下来要做什么、怎么做
-2. `工程调试指南.md` —— 已固化的调试经验与当前工程真实边界
-3. `项目技术实现.md` —— 架构、任务模型、协议模型
-4. `项目需求说明.md`
-5. `AT固件使用手册.md`
-
----
-
-## 3. 当前工程一句话状态
-
-当前项目已从早期 bring-up 阶段推进到 full-task 运行期调试阶段；`DIAG_TASK_ISOLATION=1` 稳定，`DIAG_TASK_ISOLATION=0` 仍会卡死，但故障边界已被多轮 discriminator 推进到 enabled 的 `netconn_*` 路径。当前在 `STM32F103RCT6` 上的 RAM/heap 余量过低，已被认定为调试噪声的主要来源之一，因此推荐下一阶段先切到 pin2pin 的 `STM32F103RDT6` 再继续分析。
-
----
-
-## 4. 下一位 agent 的当前目标
-
-请不要把当前任务理解成“立刻继续加逻辑修补”。当前更重要的是：
-
-1. 完成 `STM32F103RCT6 -> STM32F103RDT6` 目标切换
-2. 使用真实 Keil 日志重新确认构建成功
-3. 在新器件上复测当前代码基线
-4. 比较：
-   - 故障是否消失
-   - 是否明显后移
-   - 是否仍停在相同 enabled path
-5. 只有拿到新器件上的第一轮 RTT / heap / HWM 证据后，再决定下一步最小化改动
-
----
-
-## 5. 工作约束
-
-1. 构建真值以 `MDK-ARM/build_capture.txt`、`TCP2UART.build_log.htm`、`.map` 为准
-2. 不要再把 viewer 当作当前构建真值
-3. 不要忽视 `DIAG_TASK_ISOLATION=1 正常、=0 异常` 这个前提
-4. 在新器件的第一轮复测前，避免继续做大范围代码改动
-5. 每次只做一个能明显改变故障边界的最小改动，并保留 RTT 证据
-
----
-
-## 6. 可直接复制给下一位 agent 的起始 Prompt
-
-```text
-请先阅读：`交接清单.md`、`工程调试指南.md`、`项目技术实现.md`。
-
-当前项目是 STM32F103 + FreeRTOS + lwIP + CH390 的 TCP↔UART 透传工程。此前在 `STM32F103RCT6` 上调试时，`DIAG_TASK_ISOLATION=1` 稳定，`DIAG_TASK_ISOLATION=0` 仍会卡死，但故障边界已被多轮 discriminator 推进到 enabled 的 `netconn_*` 路径。当前最关键的资源事实是：在 `RCT6` 上 full-task 创建完四个 TCP 任务后，FreeRTOS heap 只剩约 944 bytes，静态 RAM 也已逼近物理上限，因此当前推荐先切换到 pin2pin 的 `STM32F103RDT6`，保持现有代码基线基本不变，先完成第一轮换片复测，再根据新器件上的 RTT、free/min heap 和 enabled `S1/C1` 行为决定下一步。
-
-你的当前目标不是立刻修完所有问题，而是：
-1. 完成 `RCT6 -> RDT6` 目标切换；
-2. 用真实 Keil 日志确认构建通过；
-3. 在新器件上复测当前代码，判断故障是否消失、后移或保持原状；
-4. 仅在拿到新器件上的第一轮 RTT 后，再继续做最小化的下一步判别。
-```

Core/Inc/FreeRTOSConfig.h

@@ -44,7 +44,6 @@
 
 /* USER CODE BEGIN Includes */
 /* Section where include file can be added */
-#include "debug_log.h"
 /* USER CODE END Includes */
 
 /* Ensure definitions are only used by the compiler, and not by the assembler. */
@@ -60,13 +59,13 @@
 #define configUSE_PREEMPTION                     1
 #define configSUPPORT_STATIC_ALLOCATION          1
 #define configSUPPORT_DYNAMIC_ALLOCATION         1
-#define configUSE_IDLE_HOOK                      1
+#define configUSE_IDLE_HOOK                      0
 #define configUSE_TICK_HOOK                      0
 #define configCPU_CLOCK_HZ                       ( SystemCoreClock )
 #define configTICK_RATE_HZ                       ((TickType_t)1000)
-#define configMAX_PRIORITIES                     ( 7 )
+#define configMAX_PRIORITIES                     ( 56 )
 #define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
-#define configTOTAL_HEAP_SIZE                    ((size_t)21760)
+#define configTOTAL_HEAP_SIZE                    ((size_t)8192)   /* Fit R8 RAM budget with dynamic tasks */
 #define configMAX_TASK_NAME_LEN                  ( 16 )
 #define configUSE_TRACE_FACILITY                 1
 #define configUSE_16_BIT_TICKS                   0
@@ -87,8 +86,6 @@
 #define configTIMER_TASK_PRIORITY                ( 2 )
 #define configTIMER_QUEUE_LENGTH                 10
 #define configTIMER_TASK_STACK_DEPTH             256
-#define configCHECK_FOR_STACK_OVERFLOW           2
-#define configUSE_MALLOC_FAILED_HOOK             1
 
 /* Set the following definitions to 1 to include the API function, or zero
 to exclude the API function. */
@@ -140,7 +137,7 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
 /* Normal assert() semantics without relying on the provision of an assert.h
 header file. */
 /* USER CODE BEGIN 1 */
-#define configASSERT( x ) do { if ((x) == 0) { debug_log_fault_context("config-assert", __FILE__, __LINE__); taskDISABLE_INTERRUPTS(); for( ;; ) { } } } while (0)
+#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
 /* USER CODE END 1 */
 
 /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
@@ -154,33 +151,6 @@ standard names. */
 
 /* USER CODE BEGIN Defines */
 /* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
-
-/* Application task priorities (higher number = higher priority) */
-#define TASK_PRIORITY_TCPIP                   6
-#define TASK_PRIORITY_NET_POLL                5
-#define TASK_PRIORITY_TCP_SERVER              4
-#define TASK_PRIORITY_TCP_CLIENT              4
-#define TASK_PRIORITY_UART_RX                 4
-#define TASK_PRIORITY_ROUTE                   3
-#define TASK_PRIORITY_CONFIG                  2
-#define TASK_PRIORITY_DEFAULT                 1
-
-/* Application task stack sizes (in words) */
-#define TASK_STACK_TCPIP                      512
-#define TASK_STACK_NET_POLL                   512
-#define TASK_STACK_TCP_SERVER                 512
-#define TASK_STACK_TCP_CLIENT                 512
-#define TASK_STACK_UART_RX                    384
-#define TASK_STACK_ROUTE                      512
-#define TASK_STACK_CONFIG                     384
-#define TASK_STACK_DEFAULT                    192
-
-/* Route message pool for zero-copy inter-task communication */
-#define ROUTE_MSG_POOL_SIZE                    8
-#define ROUTE_MSG_MAX_PAYLOAD                  512
-
-#define DIAG_TASK_ISOLATION                    0
-
 /* USER CODE END Defines */
 
 #endif /* FREERTOS_CONFIG_H */

Core/Inc/debug_log.h

@@ -1,26 +0,0 @@
-#ifndef DEBUG_LOG_H
-#define DEBUG_LOG_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern volatile uint32_t g_rtt_log_seq;
-extern volatile uint32_t g_rtt_log_drop_count;
-extern volatile uint32_t g_rtt_log_last_drop_seq;
-
-void debug_log_init(void);
-void debug_log_write(const char *msg);
-void debug_log_printf(const char *fmt, ...);
-void debug_log_boot(const char *tag);
-void debug_log_fault(const char *tag);
-void debug_log_runtime_snapshot(void);
-void debug_log_fault_context(const char *tag, const char *file, int line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

Core/Inc/iwdg.h

@@ -38,7 +38,7 @@ extern IWDG_HandleTypeDef hiwdg;
 
 /* USER CODE END Private defines */
 
-HAL_StatusTypeDef MX_IWDG_Init(void);
+void MX_IWDG_Init(void);
 
 /* USER CODE BEGIN Prototypes */
 

Core/Inc/main.h

@@ -51,9 +51,9 @@ extern "C" {
 
 /* Exported functions prototypes ---------------------------------------------*/
 void Error_Handler(void);
-void Debug_TrapWithRttHint(const char *tag);
 
 /* USER CODE BEGIN EFP */
+void Debug_TrapWithRttHint(const char *tag);
 
 /* USER CODE END EFP */
 

Core/Inc/stm32f1xx_hal_conf.h

@@ -64,7 +64,7 @@
 /*#define HAL_SMARTCARD_MODULE_ENABLED   */
 #define HAL_SPI_MODULE_ENABLED
 /*#define HAL_SRAM_MODULE_ENABLED   */
-/*#define HAL_TIM_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
 #define HAL_UART_MODULE_ENABLED
 /*#define HAL_USART_MODULE_ENABLED   */
 /*#define HAL_WWDG_MODULE_ENABLED   */

Core/Inc/stm32f1xx_it.h

@@ -1,31 +1,75 @@
-#ifndef __STM32F1XX_IT_H
+/* USER CODE BEGIN Header */
-#define __STM32F1XX_IT_H
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2026 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_IT_H
+#define __STM32F1xx_IT_H
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
 void NMI_Handler(void);
 void HardFault_Handler(void);
 void MemManage_Handler(void);
 void BusFault_Handler(void);
 void UsageFault_Handler(void);
 void DebugMon_Handler(void);
+void SysTick_Handler(void);
 void DMA1_Channel2_IRQHandler(void);
 void DMA1_Channel3_IRQHandler(void);
 void DMA1_Channel4_IRQHandler(void);
 void DMA1_Channel5_IRQHandler(void);
 void DMA1_Channel6_IRQHandler(void);
 void DMA1_Channel7_IRQHandler(void);
-void EXTI0_IRQHandler(void);
+void TIM4_IRQHandler(void);
 void SPI1_IRQHandler(void);
 void USART1_IRQHandler(void);
 void USART2_IRQHandler(void);
 void USART3_IRQHandler(void);
-void TIM4_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif
+#endif /* __STM32F1xx_IT_H */

Core/Inc/tim.h

@@ -0,0 +1,41 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.h
+  * @brief   This file contains all the function prototypes for the tim.c file
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TIM_H__
+#define __TIM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern TIM_HandleTypeDef htim4;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_TIM4_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_H__ */
+

Core/Inc/usart.h

@@ -47,7 +47,6 @@ void MX_USART2_UART_Init(void);
 void MX_USART3_UART_Init(void);
 
 /* USER CODE BEGIN Prototypes */
-void USART_SetConfiguredBaudrates(uint32_t usart2_baudrate, uint32_t usart3_baudrate);
 
 /* USER CODE END Prototypes */
 

Core/Src/debug_log.c

@@ -1,117 +0,0 @@
-#include "debug_log.h"
-
-#include <stdarg.h>
-#include <stdio.h>
-#include <string.h>
-#include "FreeRTOS.h"
-#include "SEGGER_RTT.h"
-#include "task.h"
-
-volatile uint32_t g_rtt_log_seq = 0u;
-volatile uint32_t g_rtt_log_drop_count = 0u;
-volatile uint32_t g_rtt_log_last_drop_seq = 0u;
-
-static void debug_backend_write(const char *msg)
-{
-    unsigned len;
-    unsigned written;
-
-    if ((msg == NULL) || (msg[0] == '\0')) {
-        return;
-    }
-
-    len = (unsigned)strlen(msg);
-    g_rtt_log_seq += 1u;
-    written = SEGGER_RTT_Write(0u, msg, len);
-    if (written < len) {
-        g_rtt_log_drop_count += 1u;
-        g_rtt_log_last_drop_seq = g_rtt_log_seq;
-    }
-}
-
-void debug_log_init(void)
-{
-    SEGGER_RTT_Init();
-}
-
-void debug_log_write(const char *msg)
-{
-    if (msg == NULL) {
-        return;
-    }
-
-    debug_backend_write(msg);
-}
-
-void debug_log_printf(const char *fmt, ...)
-{
-    char buffer[256];
-    va_list args;
-    int len;
-
-    if (fmt == NULL) {
-        return;
-    }
-
-    va_start(args, fmt);
-    len = vsnprintf(buffer, sizeof(buffer), fmt, args);
-    va_end(args);
-
-    if (len < 0) {
-        return;
-    }
-
-    buffer[sizeof(buffer) - 1u] = '\0';
-    debug_backend_write(buffer);
-}
-
-void debug_log_boot(const char *tag)
-{
-    debug_log_printf("[BOOT] %s\r\n", (tag != NULL) ? tag : "(null)");
-}
-
-void debug_log_fault(const char *tag)
-{
-    debug_log_printf("[FAULT] %s\r\n", (tag != NULL) ? tag : "(null)");
-}
-
-void debug_log_fault_context(const char *tag, const char *file, int line)
-{
-    debug_log_printf("[FAULT] %s file=%s line=%d free=%lu min=%lu seq=%lu drop=%lu last_drop=%lu\r\n",
-                     (tag != NULL) ? tag : "(null)",
-                     (file != NULL) ? file : "(null)",
-                     line,
-                     (unsigned long)xPortGetFreeHeapSize(),
-                     (unsigned long)xPortGetMinimumEverFreeHeapSize(),
-                     (unsigned long)g_rtt_log_seq,
-                     (unsigned long)g_rtt_log_drop_count,
-                     (unsigned long)g_rtt_log_last_drop_seq);
-}
-
-void debug_log_runtime_snapshot(void)
-{
-    UBaseType_t default_hwm;
-    size_t free_heap;
-    size_t min_heap;
-
-    free_heap = xPortGetFreeHeapSize();
-    min_heap = xPortGetMinimumEverFreeHeapSize();
-    default_hwm = uxTaskGetStackHighWaterMark(NULL);
-
-    debug_log_printf("[RTOS] free=%lu min=%lu self_hwm=%lu\r\n",
-                     (unsigned long)free_heap,
-                     (unsigned long)min_heap,
-                     (unsigned long)default_hwm);
-}
-
-void lwip_platform_assert(const char *msg, const char *file, int line)
-{
-    debug_log_printf("[FAULT] lwip-assert msg=%s file=%s line=%d\r\n",
-                     (msg != NULL) ? msg : "(null)",
-                     (file != NULL) ? file : "(null)",
-                     line);
-
-    taskDISABLE_INTERRUPTS();
-    while (1) {
-    }
-}

Core/Src/freertos.c

@@ -1,234 +0,0 @@
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-#include "semphr.h"
-#include "main.h"
-#include "gpio.h"
-#include "iwdg.h"
-
-#include "config.h"
-#include "debug_log.h"
-#include "route_msg.h"
-#include "app_runtime.h"
-#include "task_net_poll.h"
-#include "tcp_server.h"
-#include "tcp_client.h"
-#include "uart_trans.h"
-
-QueueHandle_t xTcpRxQueue = NULL;
-QueueHandle_t xConfigQueue = NULL;
-QueueHandle_t xLinkTxQueues[CONFIG_LINK_COUNT] = {0};
-SemaphoreHandle_t xNetSemaphore = NULL;
-
-TaskHandle_t xUartRxTaskHandle = NULL;
-TaskHandle_t xConfigTaskHandle = NULL;
-volatile BaseType_t g_netif_ready = pdFALSE;
-volatile uint32_t g_netif_phase = 0u;
-volatile int32_t g_netif_add_err = 0x7FFFFFFF;
-volatile int32_t g_netif_set_default_err = 0x7FFFFFFF;
-volatile int32_t g_netif_set_link_down_err = 0x7FFFFFFF;
-volatile int32_t g_netif_set_up_err = 0x7FFFFFFF;
-volatile int32_t g_netif_init_ok = 0;
-
-static TaskHandle_t xNetPollTaskHandle = NULL;
-static TaskHandle_t xTcpSrvTaskS1Handle = NULL;
-static TaskHandle_t xTcpSrvTaskS2Handle = NULL;
-static TaskHandle_t xTcpCliTaskC1Handle = NULL;
-static TaskHandle_t xTcpCliTaskC2Handle = NULL;
-static TaskHandle_t xDefaultTaskHandle = NULL;
-static BaseType_t xNetworkTasksStarted = pdFALSE;
-static volatile BaseType_t xNetworkTaskStopRequested = pdFALSE;
-static volatile BaseType_t xNetworkRestartRequested = pdFALSE;
-
-void app_start_network_tasks(void)
-{
-#if !DIAG_TASK_ISOLATION
-    BaseType_t rc;
-    const device_config_t *cfg;
-
-    if (xNetworkTasksStarted != pdFALSE) {
-        debug_log_write("[NET] start-network-tasks already\r\n");
-        return;
-    }
-
-    if (xNetworkTaskStopRequested != pdFALSE) {
-        debug_log_write("[NET] start-network-tasks stop-pending\r\n");
-        return;
-    }
-
-    cfg = config_get();
-
-    debug_log_printf("[NET] start-network-tasks enter free=%lu min=%lu\r\n",
-                     (unsigned long)xPortGetFreeHeapSize(),
-                     (unsigned long)xPortGetMinimumEverFreeHeapSize());
-
-    if (cfg->links[CONFIG_LINK_S1].enabled != 0u) {
-        rc = xTaskCreate(TcpSrvTask_S1, "TcpSrvS1", TASK_STACK_TCP_SERVER, NULL, TASK_PRIORITY_TCP_SERVER, &xTcpSrvTaskS1Handle);
-        debug_log_printf("[NET] create TcpSrvS1 rc=%ld free=%lu min=%lu\r\n",
-                         (long)rc,
-                         (unsigned long)xPortGetFreeHeapSize(),
-                         (unsigned long)xPortGetMinimumEverFreeHeapSize());
-        configASSERT(rc == pdPASS);
-    } else {
-        debug_log_write("[NET] skip TcpSrvS1 en=0\r\n");
-    }
-
-    if (cfg->links[CONFIG_LINK_S2].enabled != 0u) {
-        rc = xTaskCreate(TcpSrvTask_S2, "TcpSrvS2", TASK_STACK_TCP_SERVER, NULL, TASK_PRIORITY_TCP_SERVER, &xTcpSrvTaskS2Handle);
-        debug_log_printf("[NET] create TcpSrvS2 rc=%ld free=%lu min=%lu\r\n",
-                         (long)rc,
-                         (unsigned long)xPortGetFreeHeapSize(),
-                         (unsigned long)xPortGetMinimumEverFreeHeapSize());
-        configASSERT(rc == pdPASS);
-    } else {
-        debug_log_write("[NET] skip TcpSrvS2 en=0\r\n");
-    }
-
-    if (cfg->links[CONFIG_LINK_C1].enabled != 0u) {
-        rc = xTaskCreate(TcpCliTask_C1, "TcpCliC1", TASK_STACK_TCP_CLIENT, NULL, TASK_PRIORITY_TCP_CLIENT, &xTcpCliTaskC1Handle);
-        debug_log_printf("[NET] create TcpCliC1 rc=%ld free=%lu min=%lu\r\n",
-                         (long)rc,
-                         (unsigned long)xPortGetFreeHeapSize(),
-                         (unsigned long)xPortGetMinimumEverFreeHeapSize());
-        configASSERT(rc == pdPASS);
-    } else {
-        debug_log_write("[NET] skip TcpCliC1 en=0\r\n");
-    }
-
-    if (cfg->links[CONFIG_LINK_C2].enabled != 0u) {
-        rc = xTaskCreate(TcpCliTask_C2, "TcpCliC2", TASK_STACK_TCP_CLIENT, NULL, TASK_PRIORITY_TCP_CLIENT, &xTcpCliTaskC2Handle);
-        debug_log_printf("[NET] create TcpCliC2 rc=%ld free=%lu min=%lu\r\n",
-                         (long)rc,
-                         (unsigned long)xPortGetFreeHeapSize(),
-                         (unsigned long)xPortGetMinimumEverFreeHeapSize());
-        configASSERT(rc == pdPASS);
-    } else {
-        debug_log_write("[NET] skip TcpCliC2 en=0\r\n");
-    }
-
-    xNetworkTasksStarted = pdTRUE;
-
-    debug_log_printf("[NET] start-network-tasks exit free=%lu min=%lu\r\n",
-                     (unsigned long)xPortGetFreeHeapSize(),
-                     (unsigned long)xPortGetMinimumEverFreeHeapSize());
-#endif
-}
-
-void app_request_network_task_stop(void)
-{
-    xNetworkTaskStopRequested = pdTRUE;
-}
-
-void app_clear_network_task_stop(void)
-{
-    xNetworkTaskStopRequested = pdFALSE;
-}
-
-BaseType_t app_network_task_stop_requested(void)
-{
-    return xNetworkTaskStopRequested;
-}
-
-BaseType_t app_network_tasks_are_stopped(void)
-{
-    return (xTcpSrvTaskS1Handle == NULL &&
-            xTcpSrvTaskS2Handle == NULL &&
-            xTcpCliTaskC1Handle == NULL &&
-            xTcpCliTaskC2Handle == NULL) ? pdTRUE : pdFALSE;
-}
-
-void app_on_network_task_exit(TaskHandle_t task_handle)
-{
-    taskENTER_CRITICAL();
-
-    if (task_handle == xTcpSrvTaskS1Handle) {
-        xTcpSrvTaskS1Handle = NULL;
-    } else if (task_handle == xTcpSrvTaskS2Handle) {
-        xTcpSrvTaskS2Handle = NULL;
-    } else if (task_handle == xTcpCliTaskC1Handle) {
-        xTcpCliTaskC1Handle = NULL;
-    } else if (task_handle == xTcpCliTaskC2Handle) {
-        xTcpCliTaskC2Handle = NULL;
-    }
-
-    if (xTcpSrvTaskS1Handle == NULL &&
-        xTcpSrvTaskS2Handle == NULL &&
-        xTcpCliTaskC1Handle == NULL &&
-        xTcpCliTaskC2Handle == NULL) {
-        xNetworkTasksStarted = pdFALSE;
-    }
-
-    taskEXIT_CRITICAL();
-}
-
-void app_request_network_restart(void)
-{
-    xNetworkRestartRequested = pdTRUE;
-}
-
-void app_clear_network_restart_request(void)
-{
-    xNetworkRestartRequested = pdFALSE;
-}
-
-BaseType_t app_network_restart_requested(void)
-{
-    return xNetworkRestartRequested;
-}
-
-static void StartDefaultTask(void *argument)
-{
-    BaseType_t iwdg_ready = pdFALSE;
-
-    (void)argument;
-    debug_log_boot("default-task");
-
-    if (MX_IWDG_Init() == HAL_OK) {
-        debug_log_write("[BOOT] iwdg-started\r\n");
-        iwdg_ready = pdTRUE;
-    } else {
-        debug_log_write("[BOOT] iwdg-init-fail\r\n");
-    }
-
-    for (;;) {
-        HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
-        if (iwdg_ready == pdTRUE) {
-            HAL_IWDG_Refresh(&hiwdg);
-        }
-        vTaskDelay(pdMS_TO_TICKS(500));
-    }
-}
-
-void MX_FREERTOS_Init(void)
-{
-    uint32_t i;
-
-    route_msg_init();
-    configASSERT(uart_trans_init() == 0);
-    debug_log_boot("uart-trans-init");
-
-    xNetSemaphore = xSemaphoreCreateBinary();
-    xTcpRxQueue = xQueueCreate(6, sizeof(route_msg_t *));
-    xConfigQueue = xQueueCreate(2, sizeof(route_msg_t *));
-    for (i = 0; i < CONFIG_LINK_COUNT; ++i) {
-        xLinkTxQueues[i] = xQueueCreate(4, sizeof(route_msg_t *));
-    }
-
-    configASSERT(xNetSemaphore != NULL);
-    configASSERT(xTcpRxQueue != NULL);
-    configASSERT(xConfigQueue != NULL);
-    for (i = 0; i < CONFIG_LINK_COUNT; ++i) {
-        configASSERT(xLinkTxQueues[i] != NULL);
-    }
-
-    configASSERT(xTaskCreate(StartDefaultTask, "defaultTask", TASK_STACK_DEFAULT, NULL, TASK_PRIORITY_DEFAULT, &xDefaultTaskHandle) == pdPASS);
-
-    configASSERT(xTaskCreate(NetPollTask, "NetPoll", TASK_STACK_NET_POLL, NULL, TASK_PRIORITY_NET_POLL, &xNetPollTaskHandle) == pdPASS);
-#if !DIAG_TASK_ISOLATION
-    configASSERT(xTaskCreate(UartRxTask, "UartRx", TASK_STACK_UART_RX, NULL, TASK_PRIORITY_UART_RX, &xUartRxTaskHandle) == pdPASS);
-    configASSERT(xTaskCreate(ConfigTask, "Config", TASK_STACK_CONFIG, NULL, TASK_PRIORITY_CONFIG, &xConfigTaskHandle) == pdPASS);
-#else
-    debug_log_write("[DIAG] task-isolation enabled\r\n");
-#endif
-    debug_log_boot("tasks-created");
-}

Core/Src/gpio.c

@@ -56,6 +56,9 @@ void MX_GPIO_Init(void)
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1, GPIO_PIN_RESET);
 
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_SET);
+
   /*Configure GPIO pin : PC13 */
   GPIO_InitStruct.Pin = GPIO_PIN_13;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@@ -76,15 +79,16 @@ void MX_GPIO_Init(void)
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
-  /* EXTI interrupt init
+  /*Configure GPIO pin : PA4 */
-   * Keep CH390 INT masked during early boot.  PB0 may already be asserted at
+  GPIO_InitStruct.Pin = GPIO_PIN_4;
-   * power-on, while the FreeRTOS semaphore is not created until
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-   * MX_FREERTOS_Init().  The network driver enables EXTI0 after CH390 and the
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
-   * RTOS objects are ready.
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-   */
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-  HAL_NVIC_DisableIRQ(EXTI0_IRQn);
+
-  __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_0);
+  /* EXTI interrupt init*/
   HAL_NVIC_SetPriority(EXTI0_IRQn, 6, 0);
+  HAL_NVIC_EnableIRQ(EXTI0_IRQn);
 
 }
 

Core/Src/iwdg.c

@@ -27,7 +27,7 @@
 IWDG_HandleTypeDef hiwdg;
 
 /* IWDG init function */
-HAL_StatusTypeDef MX_IWDG_Init(void)
+void MX_IWDG_Init(void)
 {
 
   /* USER CODE BEGIN IWDG_Init 0 */
@@ -38,16 +38,16 @@ HAL_StatusTypeDef MX_IWDG_Init(void)
 
   /* USER CODE END IWDG_Init 1 */
   hiwdg.Instance = IWDG;
-  hiwdg.Init.Prescaler = IWDG_PRESCALER_64;
+  hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
   hiwdg.Init.Reload = 4095;
   if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
   {
-    return HAL_ERROR;
+    Error_Handler();
   }
   /* USER CODE BEGIN IWDG_Init 2 */
 
   /* USER CODE END IWDG_Init 2 */
-  return HAL_OK;
+
 }
 
 /* USER CODE BEGIN 1 */

Core/Src/main.c

@@ -4,204 +4,481 @@
   * @file           : main.c
   * @brief          : Main program body
   ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2026 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
   */
 /* USER CODE END Header */
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
-#include "cmsis_os.h"
 #include "dma.h"
 #include "iwdg.h"
 #include "spi.h"
+#include "tim.h"
 #include "usart.h"
 #include "gpio.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
 #include <stdio.h>
+#include <string.h>
 
+#include "CH390.h"
+#include "CH390_Interface.h"
+#include "SEGGER_RTT.h"
 #include "config.h"
-#include "debug_log.h"
+#include "ethernetif.h"
+#include "ch390_runtime.h"
+#include "lwip/init.h"
+#include "lwip/timeouts.h"
+#include "tcp_client.h"
+#include "tcp_server.h"
+#include "uart_trans.h"
 /* USER CODE END Includes */
 
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN PTD */
-
-/* USER CODE END PTD */
-
 /* Private define ------------------------------------------------------------*/
 /* USER CODE BEGIN PD */
-/* CH390 硬件控制引脚 */
-#define CH390_RST_PIN       GPIO_PIN_1
-#define CH390_RST_PORT      GPIOB
-#define CH390_CS_PIN        GPIO_PIN_4
-#define CH390_CS_PORT       GPIOA
-
-/* LED 指示灯 */
 #define LED_PIN             GPIO_PIN_13
 #define LED_PORT            GPIOC
+#define APP_ROUTE_BUFFER_SIZE 256u
+#define STACK_GUARD_WORD     0xA5A5A5A5u
 /* USER CODE END PD */
 
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN PM */
-
-/* USER CODE END PM */
-
 /* Private variables ---------------------------------------------------------*/
-
 /* USER CODE BEGIN PV */
-
+static volatile uint16_t g_led_blink_ticks = 0;
+static uint8_t g_clock_fallback_to_hsi = 0u;
+volatile uint8_t g_uart1_rx_probe_byte = 0u;
+static uint8_t g_stack_guard_reported = 0u;
+static uint8_t g_mux_response_frame[272];
+static uint8_t g_links_started = 0u;
 /* USER CODE END PV */
 
 /* Private function prototypes -----------------------------------------------*/
 void SystemClock_Config(void);
-void MX_FREERTOS_Init(void);
 /* USER CODE BEGIN PFP */
-static void CH390_HardwareReset(void);
 static void LED_Init(void);
-static void ApplyConfiguredUartBaudrates(void);
+static void LED_StartBlink(void);
-void Debug_TrapWithRttHint(const char *tag);
+static void BootDiag_ReportCh390(void);
+static void App_Init(void);
+static void App_Poll(void);
+static void App_ConfigureLinks(const device_config_t *cfg);
+static void App_RouteRawUartTraffic(void);
+static void App_RouteMuxUartTraffic(void);
+static void App_RouteTcpTraffic(void);
+static void StackGuard_Init(void);
+static void StackGuard_Check(void);
+static void App_SendToUart(uint8_t uart_index, uint8_t src_id, uint8_t dst_mask, const uint8_t *data, uint16_t len);
 /* USER CODE END PFP */
 
 /* Private user code ---------------------------------------------------------*/
 /* USER CODE BEGIN 0 */
+extern uint32_t Stack_Mem[];
 
-/**
- * @brief CH390 硬件复位
- * @note  复位时序: RST 低电平至少 10us，然后高电平等待 50ms 完成初始化
- */
-static void CH390_HardwareReset(void)
-{
-    /* 拉低 RST 引脚 */
-    HAL_GPIO_WritePin(CH390_RST_PORT, CH390_RST_PIN, GPIO_PIN_RESET);
-    HAL_Delay(1);  /* 保持低电平 1ms (远超最小 10us 要求) */
-    
-    /* 拉高 RST 引脚，等待芯片初始化完成 */
-    HAL_GPIO_WritePin(CH390_RST_PORT, CH390_RST_PIN, GPIO_PIN_SET);
-    HAL_Delay(50); /* 等待 50ms */
-    
-    /* 确保 CS 为高电平（未选中状态） */
-    HAL_GPIO_WritePin(CH390_CS_PORT, CH390_CS_PIN, GPIO_PIN_SET);
-}
-
-/**
- * @brief LED 初始化（点亮表示系统启动）
- */
 static void LED_Init(void)
 {
-    /* LED 灭（PC13 高电平灭，低电平亮） */
     HAL_GPIO_WritePin(LED_PORT, LED_PIN, GPIO_PIN_SET);
 }
 
-/**
+static void StackGuard_Init(void)
- * @brief LED 闪烁（用于指示系统运行状态）
+{
- */
+    Stack_Mem[0] = STACK_GUARD_WORD;
+    g_stack_guard_reported = 0u;
+}
+
+static void StackGuard_Check(void)
+{
+    if (Stack_Mem[0] != STACK_GUARD_WORD) {
+        if (g_stack_guard_reported == 0u) {
+            g_stack_guard_reported = 1u;
+            SEGGER_RTT_WriteString(0, "ERROR: Main stack guard overwritten\r\n");
+        }
+        __disable_irq();
+        NVIC_SystemReset();
+    }
+}
+
+static void LED_StartBlink(void)
+{
+    if (HAL_TIM_Base_Start_IT(&htim4) != HAL_OK) {
+        Error_Handler();
+    }
+}
+
 void LED_Toggle(void)
 {
     HAL_GPIO_TogglePin(LED_PORT, LED_PIN);
 }
 
-static void ApplyConfiguredUartBaudrates(void)
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
 {
-    USART_SetConfiguredBaudrates(config_get_uart_baudrate(LINK_UART_U0),
+    if (htim->Instance == TIM4) {
-                                 config_get_uart_baudrate(LINK_UART_U1));
+        g_led_blink_ticks++;
+        if (g_led_blink_ticks >= 1000u) {
+            g_led_blink_ticks = 0u;
+            LED_Toggle();
+        }
+    }
 }
 
+static void BootDiag_ReportCh390(void)
+{
+    ch390_diag_t diag;
+    const device_config_t *cfg = config_get();
+    uint8_t mac_hw[6];
+
+    ch390_runtime_get_diag(&diag);
+    ch390_get_mac(mac_hw);
+
+    SEGGER_RTT_printf(0,
+                      "CH390 VID=0x%04X PID=0x%04X REV=0x%02X LINK=%u MAC=%02X:%02X:%02X:%02X:%02X:%02X\r\n",
+                      diag.vendor_id,
+                      diag.product_id,
+                      diag.revision,
+                      diag.link_up,
+                      mac_hw[0], mac_hw[1], mac_hw[2], mac_hw[3], mac_hw[4], mac_hw[5]);
+    SEGGER_RTT_printf(0,
+                      "NET cfg IP=%u.%u.%u.%u MASK=%u.%u.%u.%u GW=%u.%u.%u.%u MUX=%u\r\n",
+                      cfg->net.ip[0], cfg->net.ip[1], cfg->net.ip[2], cfg->net.ip[3],
+                      cfg->net.mask[0], cfg->net.mask[1], cfg->net.mask[2], cfg->net.mask[3],
+                      cfg->net.gw[0], cfg->net.gw[1], cfg->net.gw[2], cfg->net.gw[3],
+                      cfg->mux_mode);
+}
+
+static void App_ConfigureLinks(const device_config_t *cfg)
+{
+    tcp_server_instance_config_t server_cfg;
+    tcp_client_instance_config_t client_cfg;
+
+    (void)tcp_server_init_all();
+    (void)tcp_client_init_all();
+
+    server_cfg.enabled = (cfg->links[CONFIG_LINK_S1].enabled != 0u);
+    server_cfg.port = cfg->links[CONFIG_LINK_S1].local_port;
+    (void)tcp_server_config(0u, &server_cfg);
+
+    server_cfg.enabled = (cfg->links[CONFIG_LINK_S2].enabled != 0u);
+    server_cfg.port = cfg->links[CONFIG_LINK_S2].local_port;
+    (void)tcp_server_config(1u, &server_cfg);
+
+    memcpy(client_cfg.remote_ip, cfg->links[CONFIG_LINK_C1].remote_ip, sizeof(client_cfg.remote_ip));
+    client_cfg.local_port = cfg->links[CONFIG_LINK_C1].local_port;
+    client_cfg.remote_port = cfg->links[CONFIG_LINK_C1].remote_port;
+    client_cfg.reconnect_interval_ms = TCP_CLIENT_RECONNECT_DELAY_MS;
+    client_cfg.enabled = (cfg->links[CONFIG_LINK_C1].enabled != 0u);
+    client_cfg.auto_reconnect = true;
+    (void)tcp_client_config(0u, &client_cfg);
+
+    memcpy(client_cfg.remote_ip, cfg->links[CONFIG_LINK_C2].remote_ip, sizeof(client_cfg.remote_ip));
+    client_cfg.local_port = cfg->links[CONFIG_LINK_C2].local_port;
+    client_cfg.remote_port = cfg->links[CONFIG_LINK_C2].remote_port;
+    client_cfg.enabled = (cfg->links[CONFIG_LINK_C2].enabled != 0u);
+    (void)tcp_client_config(1u, &client_cfg);
+}
+
+static void App_StartLinksIfNeeded(void)
+{
+    if ((g_links_started != 0u) || !netif_is_link_up(&ch390_netif)) {
+        return;
+    }
+
+    for (uint8_t i = 0; i < TCP_SERVER_INSTANCE_COUNT; ++i) {
+        (void)tcp_server_start(i);
+    }
+    for (uint8_t i = 0; i < TCP_CLIENT_INSTANCE_COUNT; ++i) {
+        (void)tcp_client_connect(i);
+    }
+
+    g_links_started = 1u;
+    SEGGER_RTT_WriteString(0, "NET links started after link-up\r\n");
+}
+
+static void App_StopLinksIfNeeded(void)
+{
+    if (netif_is_link_up(&ch390_netif)) {
+        return;
+    }
+
+    if (g_links_started != 0u) {
+        for (uint8_t i = 0; i < TCP_CLIENT_INSTANCE_COUNT; ++i) {
+            (void)tcp_client_disconnect(i);
+        }
+        for (uint8_t i = 0; i < TCP_SERVER_INSTANCE_COUNT; ++i) {
+            (void)tcp_server_stop(i);
+        }
+        SEGGER_RTT_WriteString(0, "NET links stopped after link-down\r\n");
+    }
+
+    g_links_started = 0u;
+}
+
+static void App_Init(void)
+{
+    const device_config_t *cfg;
+    ip4_addr_t ipaddr;
+    ip4_addr_t netmask;
+    ip4_addr_t gateway;
+    uart_config_t uart_cfg;
+
+    (void)config_init();
+    cfg = config_get();
+
+    (void)uart_trans_init();
+    uart_cfg.baudrate = cfg->uart_baudrate[0];
+    (void)uart_trans_config(UART_CHANNEL_U0, &uart_cfg);
+    uart_cfg.baudrate = cfg->uart_baudrate[1];
+    (void)uart_trans_config(UART_CHANNEL_U1, &uart_cfg);
+    (void)uart_trans_start(UART_CHANNEL_U0);
+    (void)uart_trans_start(UART_CHANNEL_U1);
+
+    SEGGER_RTT_Init();
+    StackGuard_Init();
+    SEGGER_RTT_WriteString(0, "\r\nTCP2UART boot\r\n");
+    if (g_clock_fallback_to_hsi != 0u) {
+        SEGGER_RTT_WriteString(0, "WARN: HSE start failed, fallback to HSI PLL\r\n");
+    }
+
+    lwip_init();
+    IP4_ADDR(&ipaddr, cfg->net.ip[0], cfg->net.ip[1], cfg->net.ip[2], cfg->net.ip[3]);
+    IP4_ADDR(&netmask, cfg->net.mask[0], cfg->net.mask[1], cfg->net.mask[2], cfg->net.mask[3]);
+    IP4_ADDR(&gateway, cfg->net.gw[0], cfg->net.gw[1], cfg->net.gw[2], cfg->net.gw[3]);
+    lwip_netif_init(&ipaddr, &netmask, &gateway);
+    App_ConfigureLinks(cfg);
+    BootDiag_ReportCh390();
+
+    if (HAL_UART_Receive_IT(&huart1, (uint8_t *)&g_uart1_rx_probe_byte, 1u) != HAL_OK) {
+        Error_Handler();
+    }
+}
+
+static void App_SendToUart(uint8_t uart_index, uint8_t src_id, uint8_t dst_mask, const uint8_t *data, uint16_t len)
+{
+    const device_config_t *cfg = config_get();
+    uart_channel_t channel = (uart_index == LINK_UART_U1) ? UART_CHANNEL_U1 : UART_CHANNEL_U0;
+
+    if (cfg->mux_mode == MUX_MODE_FRAME) {
+        uint8_t frame[APP_ROUTE_BUFFER_SIZE + 6u];
+        uint16_t frame_len = 0u;
+        if (uart_mux_encode_frame(src_id, dst_mask, data, len, frame, &frame_len, sizeof(frame))) {
+            (void)uart_trans_write(channel, frame, frame_len);
+        }
+    } else {
+        (void)uart_trans_write(channel, data, len);
+    }
+}
+
+static void App_RouteTcpTraffic(void)
+{
+    const device_config_t *cfg = config_get();
+    uint8_t buffer[APP_ROUTE_BUFFER_SIZE];
+
+    for (uint8_t i = 0; i < TCP_SERVER_INSTANCE_COUNT; ++i) {
+        int rc = tcp_server_recv(i, buffer, sizeof(buffer));
+        if (rc > 0) {
+            uint8_t link_index = (i == 0u) ? CONFIG_LINK_S1 : CONFIG_LINK_S2;
+            App_SendToUart(cfg->links[link_index].uart,
+                           config_link_index_to_endpoint(link_index),
+                           config_uart_index_to_endpoint(cfg->links[link_index].uart),
+                           buffer,
+                           (uint16_t)rc);
+        }
+    }
+
+    for (uint8_t i = 0; i < TCP_CLIENT_INSTANCE_COUNT; ++i) {
+        int rc = tcp_client_recv(i, buffer, sizeof(buffer));
+        if (rc > 0) {
+            uint8_t link_index = (i == 0u) ? CONFIG_LINK_C1 : CONFIG_LINK_C2;
+            App_SendToUart(cfg->links[link_index].uart,
+                           config_link_index_to_endpoint(link_index),
+                           config_uart_index_to_endpoint(cfg->links[link_index].uart),
+                           buffer,
+                           (uint16_t)rc);
+        }
+    }
+}
+
+static void App_RouteRawUartTraffic(void)
+{
+    const device_config_t *cfg = config_get();
+    uint8_t buffer[APP_ROUTE_BUFFER_SIZE];
+    uint16_t len;
+
+    len = uart_trans_read(UART_CHANNEL_U0, buffer, sizeof(buffer));
+    if (len > 0u) {
+        for (uint8_t i = 0; i < CONFIG_LINK_COUNT; ++i) {
+            if (cfg->links[i].enabled == 0u || cfg->links[i].uart != LINK_UART_U0) {
+                continue;
+            }
+            if (i == CONFIG_LINK_S1) {
+                (void)tcp_server_send(0u, buffer, len);
+            } else if (i == CONFIG_LINK_S2) {
+                (void)tcp_server_send(1u, buffer, len);
+            } else if (i == CONFIG_LINK_C1) {
+                (void)tcp_client_send(0u, buffer, len);
+            } else if (i == CONFIG_LINK_C2) {
+                (void)tcp_client_send(1u, buffer, len);
+            }
+        }
+    }
+
+    len = uart_trans_read(UART_CHANNEL_U1, buffer, sizeof(buffer));
+    if (len > 0u) {
+        for (uint8_t i = 0; i < CONFIG_LINK_COUNT; ++i) {
+            if (cfg->links[i].enabled == 0u || cfg->links[i].uart != LINK_UART_U1) {
+                continue;
+            }
+            if (i == CONFIG_LINK_S1) {
+                (void)tcp_server_send(0u, buffer, len);
+            } else if (i == CONFIG_LINK_S2) {
+                (void)tcp_server_send(1u, buffer, len);
+            } else if (i == CONFIG_LINK_C1) {
+                (void)tcp_client_send(0u, buffer, len);
+            } else if (i == CONFIG_LINK_C2) {
+                (void)tcp_client_send(1u, buffer, len);
+            }
+        }
+    }
+}
+
+static void App_RouteMuxUartTraffic(void)
+{
+    uart_mux_frame_t frame;
+    const device_config_t *cfg = config_get();
+
+    while (uart_mux_try_extract_frame(UART_CHANNEL_U0, &frame)) {
+        SEGGER_RTT_printf(0, "Mux frame from UART0: src_id=%u dst_mask=0x%02X len=%u\r\n", frame.src_id, frame.dst_mask, frame.payload_len);
+        if (frame.dst_mask == 0u) {
+            at_result_t result;
+            char *response_text = (char *)&g_mux_response_frame[5];
+            if (config_build_response_frame(frame.payload, frame.payload_len, response_text, (uint16_t)(sizeof(g_mux_response_frame) - 6u), &result)) {
+                uint16_t response_len = (uint16_t)strlen(response_text);
+                uint16_t frame_len = 0u;
+                if (uart_mux_encode_frame(config_uart_index_to_endpoint(LINK_UART_U0), 0u, (const uint8_t *)response_text, response_len, g_mux_response_frame, &frame_len, sizeof(g_mux_response_frame))) {
+                    (void)uart_trans_write(UART_CHANNEL_U0, g_mux_response_frame, frame_len);
+                }
+                if (result == AT_NEED_REBOOT) {
+                    static const char hint[] = "Note: Use AT+SAVE then AT+RESET to apply changes\r\n";
+                    response_len = (uint16_t)strlen(hint);
+                    if (uart_mux_encode_frame(config_uart_index_to_endpoint(LINK_UART_U0), 0u, (const uint8_t *)hint, response_len, g_mux_response_frame, &frame_len, sizeof(g_mux_response_frame))) {
+                        (void)uart_trans_write(UART_CHANNEL_U0, g_mux_response_frame, frame_len);
+                    }
+                }
+            }
+            continue;
+        }
+
+        if ((frame.dst_mask & ENDPOINT_S1) != 0u) {
+            (void)tcp_server_send(0u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_S2) != 0u) {
+            (void)tcp_server_send(1u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_C1) != 0u) {
+            (void)tcp_client_send(0u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_C2) != 0u) {
+            (void)tcp_client_send(1u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_UART3) != 0u && cfg->links[CONFIG_LINK_S2].uart == LINK_UART_U1) {
+            App_SendToUart(LINK_UART_U1, frame.src_id, ENDPOINT_UART3, frame.payload, frame.payload_len);
+        }
+    }
+
+    while (uart_mux_try_extract_frame(UART_CHANNEL_U1, &frame)) {
+        SEGGER_RTT_printf(0, "Mux frame from UART1: src_id=%u dst_mask=0x%02X len=%u\r\n", frame.src_id, frame.dst_mask, frame.payload_len);
+        if (frame.dst_mask == 0u) {
+            at_result_t result;
+            char *response_text = (char *)&g_mux_response_frame[5];
+            if (config_build_response_frame(frame.payload, frame.payload_len, response_text, (uint16_t)(sizeof(g_mux_response_frame) - 6u), &result)) {
+                uint16_t response_len = (uint16_t)strlen(response_text);
+                uint16_t frame_len = 0u;
+                if (uart_mux_encode_frame(config_uart_index_to_endpoint(LINK_UART_U1), 0u, (const uint8_t *)response_text, response_len, g_mux_response_frame, &frame_len, sizeof(g_mux_response_frame))) {
+                    (void)uart_trans_write(UART_CHANNEL_U1, g_mux_response_frame, frame_len);
+                }
+                if (result == AT_NEED_REBOOT) {
+                    static const char hint[] = "Note: Use AT+SAVE then AT+RESET to apply changes\r\n";
+                    response_len = (uint16_t)strlen(hint);
+                    if (uart_mux_encode_frame(config_uart_index_to_endpoint(LINK_UART_U1), 0u, (const uint8_t *)hint, response_len, g_mux_response_frame, &frame_len, sizeof(g_mux_response_frame))) {
+                        (void)uart_trans_write(UART_CHANNEL_U1, g_mux_response_frame, frame_len);
+                    }
+                }
+            }
+            continue;
+        }
+
+        if ((frame.dst_mask & ENDPOINT_S1) != 0u) {
+            (void)tcp_server_send(0u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_S2) != 0u) {
+            (void)tcp_server_send(1u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_C1) != 0u) {
+            (void)tcp_client_send(0u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_C2) != 0u) {
+            (void)tcp_client_send(1u, frame.payload, frame.payload_len);
+        }
+        if ((frame.dst_mask & ENDPOINT_UART2) != 0u) {
+            App_SendToUart(LINK_UART_U0, frame.src_id, ENDPOINT_UART2, frame.payload, frame.payload_len);
+        }
+    }
+}
+
+static void App_Poll(void)
+{
+    ethernetif_poll();
+    ethernetif_check_link();
+    sys_check_timeouts();
+    App_StopLinksIfNeeded();
+    App_StartLinksIfNeeded();
+    tcp_client_poll();
+    uart_trans_poll();
+    StackGuard_Check();
+    config_poll();
+    App_RouteTcpTraffic();
+
+    if (config_get()->mux_mode == MUX_MODE_FRAME) {
+        App_RouteMuxUartTraffic();
+    } else {
+        App_RouteRawUartTraffic();
+    }
+
+    if (config_is_reset_requested()) {
+        config_clear_reset_requested();
+        NVIC_SystemReset();
+    }
+
+    if (hiwdg.Instance == IWDG) {
+        HAL_IWDG_Refresh(&hiwdg);
+    }
+}
 /* USER CODE END 0 */
 
-/**
-  * @brief  The application entry point.
-  * @retval int
-  */
 int main(void)
 {
-
-  /* USER CODE BEGIN 1 */
-
-  /* USER CODE END 1 */
-
-  /* MCU Configuration--------------------------------------------------------*/
-
-  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
   HAL_Init();
-
-  /* USER CODE BEGIN Init */
-  debug_log_init();
-  debug_log_boot("hal-init");
-  /* USER CODE END Init */
-
-  /* Configure the system clock */
   SystemClock_Config();
-
-  /* USER CODE BEGIN SysInit */
-  debug_log_boot("clock-config");
-  /* USER CODE END SysInit */
-
-  /* Initialize all configured peripherals */
   MX_GPIO_Init();
   MX_DMA_Init();
   MX_USART1_UART_Init();
-  config_init();
-  ApplyConfiguredUartBaudrates();
   MX_USART2_UART_Init();
   MX_USART3_UART_Init();
   MX_SPI1_Init();
-  /* USER CODE BEGIN 2 */
+  MX_TIM4_Init();
-  debug_log_boot("peripherals-ready");
 
-  /* LED 初始化 */
   LED_Init();
+  LED_StartBlink();
+  App_Init();
 
-  /* CH390 硬件复位 */
-  CH390_HardwareReset();
-  
-  debug_log_boot("config-ready");
-  
-  /* USER CODE END 2 */
-
-  /* Init scheduler */
-  osKernelInitialize();  /* Call init function for freertos objects (in cmsis_os2.c) */
-  MX_FREERTOS_Init();
-  debug_log_boot("freertos-init");
-
-  /* Start scheduler */
-  debug_log_boot("scheduler-start");
-  osKernelStart();
-
-  /* We should never get here as control is now taken by the scheduler */
-
-  /* Infinite loop */
-  /* USER CODE BEGIN WHILE */
   while (1)
   {
-    /* USER CODE END WHILE */
+    App_Poll();
-
-    /* USER CODE BEGIN 3 */
   }
-  /* USER CODE END 3 */
 }
 
-/**
-  * @brief System Clock Configuration
-  * @retval None
-  */
 void SystemClock_Config(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Initializes the RCC Oscillators according to the specified parameters
+  g_clock_fallback_to_hsi = 0u;
-  * in the RCC_OscInitTypeDef structure.
-  */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
   RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
@@ -210,13 +487,20 @@ void SystemClock_Config(void)
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
   RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-  {
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+    RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
       Error_Handler();
     }
+    g_clock_fallback_to_hsi = 1u;
+  }
 
-  /** Initializes the CPU, AHB and APB buses clocks
-  */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -230,67 +514,43 @@ void SystemClock_Config(void)
   }
 }
 
-/* USER CODE BEGIN 4 */
+#ifdef __GNUC__
+int _write(int file, char *ptr, int len)
+{
+    (void)file;
+    return (int)SEGGER_RTT_Write(0, ptr, (unsigned)len);
+}
+#else
+int fputc(int ch, FILE *f)
+{
+    (void)f;
+    SEGGER_RTT_PutChar(0, (char)ch);
+    return ch;
+}
+#endif
 
-/**
- * @brief  重定向 printf 到 UART1（调试输出）
- */
 void Debug_TrapWithRttHint(const char *tag)
 {
-  debug_log_fault_context(tag, __FILE__, __LINE__);
+    SEGGER_RTT_WriteString(0, "\r\nTRAP: ");
-}
+    SEGGER_RTT_WriteString(0, tag);
-
+    SEGGER_RTT_WriteString(0, "\r\n");
-void vApplicationMallocFailedHook(void)
-{
-  debug_log_fault_context("malloc-failed", __FILE__, __LINE__);
-  __disable_irq();
-  for (;;)
-  {
-  }
-}
-
-void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName)
-{
-  debug_log_printf("[FAULT] stack-overflow task=%s\r\n",
-                   (pcTaskName != NULL) ? pcTaskName : "(null)");
-  debug_log_fault_context("stack-overflow", __FILE__, __LINE__);
-  (void)xTask;
-  __disable_irq();
-  for (;;)
-  {
-  }
-}
-
-/* USER CODE END 4 */
-
-/**
-  * @brief  This function is executed in case of error occurrence.
-  * @retval None
-  */
-void Error_Handler(void)
-{
-  /* USER CODE BEGIN Error_Handler_Debug */
-  /* User can add his own implementation to report the HAL error return state */
-  debug_log_fault_context("error-handler", __FILE__, __LINE__);
     __disable_irq();
+    __BKPT(0);
     while (1)
     {
     }
-  /* USER CODE END Error_Handler_Debug */
 }
+
+void Error_Handler(void)
+{
+  Debug_TrapWithRttHint("Error_Handler");
+}
+
 #ifdef USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
 void assert_failed(uint8_t *file, uint32_t line)
 {
-  /* USER CODE BEGIN 6 */
+  (void)file;
-  /* User can add his own implementation to report the file name and line number,
+  (void)line;
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  Debug_TrapWithRttHint("assert_failed");
-  /* USER CODE END 6 */
 }
-#endif /* USE_FULL_ASSERT */
+#endif

Core/Src/retarget_rtt.c

@@ -1,118 +0,0 @@
-#include <rt_sys.h>
-#include <stdio.h>
-#include <string.h>
-
-#pragma import(__use_no_semihosting)
-
-const char __stdin_name[] = ":tt";
-const char __stdout_name[] = ":tt";
-const char __stderr_name[] = ":tt";
-
-#define NULL_FH_STDIN   0x8001
-#define NULL_FH_STDOUT  0x8002
-#define NULL_FH_STDERR  0x8003
-
-static int rtt_is_terminal_name(const char *name)
-{
-    return (name != NULL) && (strcmp(name, ":tt") == 0);
-}
-
-FILEHANDLE _sys_open(const char *name, int openmode)
-{
-    if (!rtt_is_terminal_name(name)) {
-        return -1;
-    }
-
-    if ((openmode & OPEN_W) == OPEN_W) {
-        return NULL_FH_STDOUT;
-    }
-
-    if ((openmode & OPEN_A) == OPEN_A) {
-        return NULL_FH_STDERR;
-    }
-
-    return NULL_FH_STDIN;
-}
-
-int _sys_close(FILEHANDLE fh)
-{
-    (void)fh;
-    return 0;
-}
-
-int _sys_write(FILEHANDLE fh, const unsigned char *buf, unsigned len, int mode)
-{
-    (void)mode;
-
-    if ((fh != NULL_FH_STDOUT) && (fh != NULL_FH_STDERR)) {
-        return -1;
-    }
-
-    if ((buf == NULL) || (len == 0u)) {
-        return 0;
-    }
-
-    (void)buf;
-    (void)len;
-    return 0;
-}
-
-int _sys_read(FILEHANDLE fh, unsigned char *buf, unsigned len, int mode)
-{
-    (void)fh;
-    (void)buf;
-    (void)len;
-    (void)mode;
-    return -1;
-}
-
-int _sys_istty(FILEHANDLE fh)
-{
-    return (fh == NULL_FH_STDIN) || (fh == NULL_FH_STDOUT) || (fh == NULL_FH_STDERR);
-}
-
-int _sys_seek(FILEHANDLE fh, long pos)
-{
-    (void)fh;
-    (void)pos;
-    return -1;
-}
-
-int _sys_ensure(FILEHANDLE fh)
-{
-    (void)fh;
-    return 0;
-}
-
-long _sys_flen(FILEHANDLE fh)
-{
-    (void)fh;
-    return 0;
-}
-
-int _sys_tmpnam(char *name, int sig, unsigned maxlen)
-{
-    (void)name;
-    (void)sig;
-    (void)maxlen;
-    return 0;
-}
-
-char *_sys_command_string(char *cmd, int len)
-{
-    (void)cmd;
-    (void)len;
-    return NULL;
-}
-
-void _ttywrch(int ch)
-{
-    (void)ch;
-}
-
-void _sys_exit(int returncode)
-{
-    (void)returncode;
-    while (1) {
-    }
-}

Core/Src/spi.c

@@ -41,10 +41,10 @@ void MX_SPI1_Init(void)
   hspi1.Init.Mode = SPI_MODE_MASTER;
   hspi1.Init.Direction = SPI_DIRECTION_2LINES;
   hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
-  hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;   /* CH390 requires CPOL=High (Mode 3) */
+  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;    /* Match CH390 runtime baseline: CPOL=Low */
-  hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;        /* CH390 requires CPHA=2Edge (Mode 3) */
+  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;        /* Match CH390 runtime baseline: CPHA=1Edge (Mode 0) */
   hspi1.Init.NSS = SPI_NSS_SOFT;                /* Software CS control for CH390 */
-  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; /* 72MHz/8 = 9MHz (CH390 max 10MHz) */
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; /* 72MHz/2 = 36MHz, max SPI1 clock at current APB2 */
   hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
   hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
   hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@@ -73,7 +73,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
 
     __HAL_RCC_GPIOA_CLK_ENABLE();
     /**SPI1 GPIO Configuration
-    PA4     ------> CH390 CS (GPIO Output, controlled by CH390_Interface.c)
+    PA4     ------> GPIO_Output
     PA5     ------> SPI1_SCK
     PA6     ------> SPI1_MISO
     PA7     ------> SPI1_MOSI
@@ -90,7 +90,11 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
     GPIO_InitStruct.Pull = GPIO_NOPULL;
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
     
-    /* PA4 (CS) is configured as GPIO output in CH390_Interface.c */
+    GPIO_InitStruct.Pin = GPIO_PIN_4;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
     /* SPI1 interrupt Init */
     HAL_NVIC_SetPriority(SPI1_IRQn, 5, 0);
@@ -113,12 +117,12 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
     __HAL_RCC_SPI1_CLK_DISABLE();
 
     /**SPI1 GPIO Configuration
-    PA4     ------> CH390 CS (handled by CH390_Interface.c)
+    PA4     ------> GPIO_Output
     PA5     ------> SPI1_SCK
     PA6     ------> SPI1_MISO
     PA7     ------> SPI1_MOSI
     */
-    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
 
     /* SPI1 interrupt Deinit */
     HAL_NVIC_DisableIRQ(SPI1_IRQn);

Core/Src/stm32f1xx_hal_msp.c

@@ -71,8 +71,6 @@ void HAL_MspInit(void)
   __HAL_RCC_PWR_CLK_ENABLE();
 
   /* System interrupt init*/
-  /* PendSV_IRQn interrupt configuration */
-  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
 
   /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
   */

Core/Src/stm32f1xx_hal_timebase_tim.c

@@ -1,47 +0,0 @@
-#include "stm32f1xx_hal.h"
-
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
-    RCC_ClkInitTypeDef clkconfig;
-    uint32_t pFLatency;
-    uint32_t uwTimclock;
-    uint32_t uwPrescalerValue;
-
-    __HAL_RCC_TIM4_CLK_ENABLE();
-
-    HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
-    uwTimclock = HAL_RCC_GetPCLK1Freq();
-    if (clkconfig.APB1CLKDivider != RCC_HCLK_DIV1) {
-        uwTimclock *= 2u;
-    }
-
-    uwPrescalerValue = (uwTimclock / 1000000u) - 1u;
-
-    TIM4->PSC = uwPrescalerValue;
-    TIM4->ARR = 1000u - 1u;
-    TIM4->EGR = TIM_EGR_UG;
-    TIM4->DIER |= TIM_DIER_UIE;
-    TIM4->CR1 |= TIM_CR1_CEN;
-
-    HAL_NVIC_SetPriority(TIM4_IRQn, TickPriority, 0u);
-    HAL_NVIC_EnableIRQ(TIM4_IRQn);
-    return HAL_OK;
-}
-
-HAL_StatusTypeDef HAL_DeInitTick(void)
-{
-    TIM4->CR1 &= ~TIM_CR1_CEN;
-    TIM4->DIER &= ~TIM_DIER_UIE;
-    HAL_NVIC_DisableIRQ(TIM4_IRQn);
-    return HAL_OK;
-}
-
-void HAL_SuspendTick(void)
-{
-    TIM4->DIER &= ~TIM_DIER_UIE;
-}
-
-void HAL_ResumeTick(void)
-{
-    TIM4->DIER |= TIM_DIER_UIE;
-}

Core/Src/stm32f1xx_it.c

@@ -1,16 +1,20 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
 #include "main.h"
 #include "stm32f1xx_it.h"
-
+#include "ethernetif.h"
-#include "FreeRTOS.h"
-#include "semphr.h"
-#include "task.h"
-
-#include "app_runtime.h"
-#include "config.h"
-#include "debug_log.h"
 #include "uart_trans.h"
+#include "config.h"
 
 extern SPI_HandleTypeDef hspi1;
+extern TIM_HandleTypeDef htim4;
 extern DMA_HandleTypeDef hdma_usart1_rx;
 extern DMA_HandleTypeDef hdma_usart1_tx;
 extern DMA_HandleTypeDef hdma_usart2_rx;
@@ -20,39 +24,31 @@ extern DMA_HandleTypeDef hdma_usart3_tx;
 extern UART_HandleTypeDef huart1;
 extern UART_HandleTypeDef huart2;
 extern UART_HandleTypeDef huart3;
+extern volatile uint8_t g_uart1_rx_probe_byte;
 
 void NMI_Handler(void)
 {
-    while (1) {
+  Debug_TrapWithRttHint("NMI_Handler");
-    }
 }
 
 void HardFault_Handler(void)
 {
-    Debug_TrapWithRttHint("hardfault");
+  Debug_TrapWithRttHint("HardFault_Handler");
-    while (1) {
-    }
 }
 
 void MemManage_Handler(void)
 {
-    Debug_TrapWithRttHint("memmanage");
+  Debug_TrapWithRttHint("MemManage_Handler");
-    while (1) {
-    }
 }
 
 void BusFault_Handler(void)
 {
-    Debug_TrapWithRttHint("busfault");
+  Debug_TrapWithRttHint("BusFault_Handler");
-    while (1) {
-    }
 }
 
 void UsageFault_Handler(void)
 {
-    Debug_TrapWithRttHint("usagefault");
+  Debug_TrapWithRttHint("UsageFault_Handler");
-    while (1) {
-    }
 }
 
 void DebugMon_Handler(void)
@@ -61,9 +57,7 @@ void DebugMon_Handler(void)
 
 void SysTick_Handler(void)
 {
-    if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
+  HAL_IncTick();
-        xPortSysTickHandler();
-    }
 }
 
 void DMA1_Channel2_IRQHandler(void)
@@ -96,18 +90,9 @@ void DMA1_Channel7_IRQHandler(void)
   HAL_DMA_IRQHandler(&hdma_usart2_tx);
 }
 
-void EXTI0_IRQHandler(void)
+void TIM4_IRQHandler(void)
 {
-    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+  HAL_TIM_IRQHandler(&htim4);
-
-    if (__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_0) != RESET) {
-        __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_0);
-        if ((xNetSemaphore != NULL) &&
-            (xTaskGetSchedulerState() == taskSCHEDULER_RUNNING)) {
-            xSemaphoreGiveFromISR(xNetSemaphore, &xHigherPriorityTaskWoken);
-            portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
-        }
-    }
 }
 
 void SPI1_IRQHandler(void)
@@ -117,48 +102,75 @@ void SPI1_IRQHandler(void)
 
 void USART1_IRQHandler(void)
 {
-    if (__HAL_UART_GET_FLAG(&huart1, UART_FLAG_IDLE) != RESET) {
-        __HAL_UART_CLEAR_IDLEFLAG(&huart1);
-        config_uart_idle_handler();
-    }
   HAL_UART_IRQHandler(&huart1);
 }
 
 void USART2_IRQHandler(void)
 {
-    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+  if (__HAL_UART_GET_FLAG(&huart2, UART_FLAG_IDLE))
-    if (__HAL_UART_GET_FLAG(&huart2, UART_FLAG_IDLE) != RESET) {
+  {
     __HAL_UART_CLEAR_IDLEFLAG(&huart2);
-        uart_trans_notify_rx_from_isr(UART_CHANNEL_U0, &xHigherPriorityTaskWoken);
+    uart_trans_idle_handler(UART_CHANNEL_U0);
-        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
   }
   HAL_UART_IRQHandler(&huart2);
 }
 
 void USART3_IRQHandler(void)
 {
-    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+  if (__HAL_UART_GET_FLAG(&huart3, UART_FLAG_IDLE))
-    if (__HAL_UART_GET_FLAG(&huart3, UART_FLAG_IDLE) != RESET) {
+  {
     __HAL_UART_CLEAR_IDLEFLAG(&huart3);
-        uart_trans_notify_rx_from_isr(UART_CHANNEL_U1, &xHigherPriorityTaskWoken);
+    uart_trans_idle_handler(UART_CHANNEL_U1);
-        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
   }
   HAL_UART_IRQHandler(&huart3);
 }
 
-void TIM4_IRQHandler(void)
+void EXTI0_IRQHandler(void)
 {
-    if ((TIM4->SR & TIM_SR_UIF) != 0u) {
+  if (__HAL_GPIO_EXTI_GET_IT(GPIO_PIN_0))
-        TIM4->SR &= ~TIM_SR_UIF;
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_0);
+    ethernetif_set_irq_pending();
   }
-    HAL_IncTick();
 }
 
 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
 {
-    if (huart == &huart2) {
+  if (huart == &huart2)
+  {
     uart_trans_tx_cplt_handler(UART_CHANNEL_U0);
-    } else if (huart == &huart3) {
+  }
+  else if (huart == &huart3)
+  {
     uart_trans_tx_cplt_handler(UART_CHANNEL_U1);
   }
 }
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  if (huart == &huart1)
+  {
+    config_uart_rx_byte(g_uart1_rx_probe_byte);
+    (void)HAL_UART_Receive_IT(&huart1, (uint8_t *)&g_uart1_rx_probe_byte, 1u);
+  }
+  else if (huart == &huart2)
+  {
+    uart_trans_rx_cplt_handler(UART_CHANNEL_U0);
+  }
+  else if (huart == &huart3)
+  {
+    uart_trans_rx_cplt_handler(UART_CHANNEL_U1);
+  }
+}
+
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  if (huart == &huart2)
+  {
+    uart_trans_rx_half_cplt_handler(UART_CHANNEL_U0);
+  }
+  else if (huart == &huart3)
+  {
+    uart_trans_rx_half_cplt_handler(UART_CHANNEL_U1);
+  }
+}

Core/Src/syscalls.c

@@ -0,0 +1,245 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeMX
+ * @brief     Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib or Picolibc libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2020-2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include "main.h"
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdio.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+
+/* Variables */
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+  return 1;
+}
+
+int _kill(int pid, int sig)
+{
+  (void)pid;
+  (void)sig;
+  errno = EINVAL;
+  return -1;
+}
+
+void _exit (int status)
+{
+  _kill(status, -1);
+  Debug_TrapWithRttHint("_exit");
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+  (void)file;
+  int DataIdx;
+
+  for (DataIdx = 0; DataIdx < len; DataIdx++)
+  {
+    *ptr++ = __io_getchar();
+  }
+
+  return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+  (void)file;
+  int DataIdx;
+
+  for (DataIdx = 0; DataIdx < len; DataIdx++)
+  {
+    __io_putchar(*ptr++);
+  }
+  return len;
+}
+
+int _close(int file)
+{
+  (void)file;
+  return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+  (void)file;
+  st->st_mode = S_IFCHR;
+  return 0;
+}
+
+int _isatty(int file)
+{
+  (void)file;
+  return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+  (void)file;
+  (void)ptr;
+  (void)dir;
+  return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+  (void)path;
+  (void)flags;
+  /* Pretend like we always fail */
+  return -1;
+}
+
+int _wait(int *status)
+{
+  (void)status;
+  errno = ECHILD;
+  return -1;
+}
+
+int _unlink(char *name)
+{
+  (void)name;
+  errno = ENOENT;
+  return -1;
+}
+
+clock_t _times(struct tms *buf)
+{
+  (void)buf;
+  return -1;
+}
+
+int _stat(const char *file, struct stat *st)
+{
+  (void)file;
+  st->st_mode = S_IFCHR;
+  return 0;
+}
+
+int _link(char *old, char *new)
+{
+  (void)old;
+  (void)new;
+  errno = EMLINK;
+  return -1;
+}
+
+int _fork(void)
+{
+  errno = EAGAIN;
+  return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+  (void)name;
+  (void)argv;
+  (void)env;
+  errno = ENOMEM;
+  return -1;
+}
+
+// --- Picolibc Specific Section ---
+#if defined(__PICOLIBC__)
+
+/**
+ * @brief Picolibc helper function to output a character to a FILE stream.
+ *        This redirects the output to the low-level __io_putchar function.
+ * @param c Character to write.
+ * @param file FILE stream pointer (ignored).
+ * @retval int The character written.
+ */
+static int starm_putc(char c, FILE *file)
+{
+	(void) file;
+  __io_putchar(c);
+	return c;
+}
+
+/**
+ * @brief Picolibc helper function to input a character from a FILE stream.
+ *        This redirects the input from the low-level __io_getchar function.
+ * @param file FILE stream pointer (ignored).
+ * @retval int The character read, cast to an unsigned char then int.
+ */
+static int starm_getc(FILE *file)
+{
+	unsigned char c;
+	(void) file;
+  c = __io_getchar();
+	return c;
+}
+
+// Define and initialize the standard I/O streams for Picolibc.
+// FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure.
+// _FDEV_SETUP_RW indicates the stream is for reading and writing.
+static FILE __stdio = FDEV_SETUP_STREAM(starm_putc,
+					starm_getc,
+					NULL,
+					_FDEV_SETUP_RW);
+
+// Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream.
+// Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.).
+FILE *const stdin = &__stdio;
+__strong_reference(stdin, stdout);
+__strong_reference(stdin, stderr);
+
+// Create strong aliases mapping standard C library function names (without underscore)
+// to the implemented system call stubs (with underscore). Picolibc uses these
+// standard names internally, so this linking is required.
+__strong_reference(_read, read);
+__strong_reference(_write, write);
+__strong_reference(_times, times);
+__strong_reference(_execve, execve);
+__strong_reference(_fork, fork);
+__strong_reference(_link, link);
+__strong_reference(_unlink, unlink);
+__strong_reference(_stat, stat);
+__strong_reference(_wait, wait);
+__strong_reference(_open, open);
+__strong_reference(_close, close);
+__strong_reference(_lseek, lseek);
+__strong_reference(_isatty, isatty);
+__strong_reference(_fstat, fstat);
+__strong_reference(_exit, exit);
+__strong_reference(_kill, kill);
+__strong_reference(_getpid, getpid);
+
+#endif //__PICOLIBC__

Core/Src/sysmem.c

@@ -0,0 +1,87 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Generated by STM32CubeMX
+ * @brief     System Memory calls file
+ *
+ *            For more information about which C functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib or Picolibc libc manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include <errno.h>
+#include <stdint.h>
+#include <stddef.h>
+
+/**
+ * Pointer to the current high watermark of the heap usage
+ */
+static uint8_t *__sbrk_heap_end = NULL;
+
+/**
+ * @brief _sbrk() allocates memory to the newlib heap and is used by malloc
+ *        and others from the C library
+ *
+ * @verbatim
+ * ############################################################################
+ * #  .data  #  .bss  #       newlib heap       #          MSP stack          #
+ * #         #        #                         # Reserved by _Min_Stack_Size #
+ * ############################################################################
+ * ^-- RAM start      ^-- _end                             _estack, RAM end --^
+ * @endverbatim
+ *
+ * This implementation starts allocating at the '_end' linker symbol
+ * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
+ * The implementation considers '_estack' linker symbol to be RAM end
+ * NOTE: If the MSP stack, at any point during execution, grows larger than the
+ * reserved size, please increase the '_Min_Stack_Size'.
+ *
+ * @param incr Memory size
+ * @return Pointer to allocated memory
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+  extern uint8_t _end; /* Symbol defined in the linker script */
+  extern uint8_t _estack; /* Symbol defined in the linker script */
+  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+  const uint8_t *max_heap = (uint8_t *)stack_limit;
+  uint8_t *prev_heap_end;
+
+  /* Initialize heap end at first call */
+  if (NULL == __sbrk_heap_end)
+  {
+    __sbrk_heap_end = &_end;
+  }
+
+  /* Protect heap from growing into the reserved MSP stack */
+  if (__sbrk_heap_end + incr > max_heap)
+  {
+    errno = ENOMEM;
+    return (void *)-1;
+  }
+
+  prev_heap_end = __sbrk_heap_end;
+  __sbrk_heap_end += incr;
+
+  return (void *)prev_heap_end;
+}
+
+#if defined(__PICOLIBC__)
+  // Picolibc expects syscalls without the leading underscore.
+  // This creates a strong alias so that
+  // calls to `sbrk()` are resolved to our `_sbrk()` implementation.
+  __strong_reference(_sbrk, sbrk);
+#endif

Core/Src/tim.c

@@ -0,0 +1,100 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.c
+  * @brief   This file provides code for the configuration of the TIM instances.
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "tim.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+TIM_HandleTypeDef htim4;
+
+/* TIM4 init function */
+void MX_TIM4_Init(void)
+{
+
+  /* USER CODE BEGIN TIM4_Init 0 */
+
+  /* USER CODE END TIM4_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM4_Init 1 */
+
+  /* USER CODE END TIM4_Init 1 */
+  htim4.Instance = TIM4;
+  htim4.Init.Prescaler = 7199;
+  htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim4.Init.Period = 9;
+  htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM4_Init 2 */
+
+  /* USER CODE END TIM4_Init 2 */
+
+}
+
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  if(tim_baseHandle->Instance==TIM4)
+  {
+  /* USER CODE BEGIN TIM4_MspInit 0 */
+
+  /* USER CODE END TIM4_MspInit 0 */
+    /* TIM4 clock enable */
+    __HAL_RCC_TIM4_CLK_ENABLE();
+
+    /* TIM4 interrupt Init */
+    HAL_NVIC_SetPriority(TIM4_IRQn, 6, 0);
+    HAL_NVIC_EnableIRQ(TIM4_IRQn);
+  /* USER CODE BEGIN TIM4_MspInit 1 */
+
+  /* USER CODE END TIM4_MspInit 1 */
+  }
+}
+
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  if(tim_baseHandle->Instance==TIM4)
+  {
+  /* USER CODE BEGIN TIM4_MspDeInit 0 */
+
+  /* USER CODE END TIM4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM4_CLK_DISABLE();
+
+    /* TIM4 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(TIM4_IRQn);
+  /* USER CODE BEGIN TIM4_MspDeInit 1 */
+
+  /* USER CODE END TIM4_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */

Core/Src/usart.c

@@ -22,9 +22,6 @@
 
 /* USER CODE BEGIN 0 */
 
-static uint32_t g_usart2_baudrate = 115200u;
-static uint32_t g_usart3_baudrate = 115200u;
-
 /* USER CODE END 0 */
 
 UART_HandleTypeDef huart1;
@@ -79,7 +76,7 @@ void MX_USART2_UART_Init(void)
 
   /* USER CODE END USART2_Init 1 */
   huart2.Instance = USART2;
-  huart2.Init.BaudRate = g_usart2_baudrate;
+  huart2.Init.BaudRate = 115200;
   huart2.Init.WordLength = UART_WORDLENGTH_8B;
   huart2.Init.StopBits = UART_STOPBITS_1;
   huart2.Init.Parity = UART_PARITY_NONE;
@@ -108,7 +105,7 @@ void MX_USART3_UART_Init(void)
 
   /* USER CODE END USART3_Init 1 */
   huart3.Instance = USART3;
-  huart3.Init.BaudRate = g_usart3_baudrate;
+  huart3.Init.BaudRate = 115200;
   huart3.Init.WordLength = UART_WORDLENGTH_8B;
   huart3.Init.StopBits = UART_STOPBITS_1;
   huart3.Init.Parity = UART_PARITY_NONE;
@@ -399,10 +396,4 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
 
 /* USER CODE BEGIN 1 */
 
-void USART_SetConfiguredBaudrates(uint32_t usart2_baudrate, uint32_t usart3_baudrate)
-{
-  g_usart2_baudrate = usart2_baudrate;
-  g_usart3_baudrate = usart3_baudrate;
-}
-
 /* USER CODE END 1 */

Drivers/CH390/CH390.c

@@ -12,74 +12,7 @@
 #include "CH390.h"
 #include "CH390_Interface.h"
 
-#define CH390_EPCR_POLL_LIMIT 100000u
+#define CH390_PHY_BUSY_TIMEOUT_LOOPS 2000u
-
-static int ch390_wait_epcr_ready(void)
-{
-    uint32_t poll_count = CH390_EPCR_POLL_LIMIT;
-
-    while ((ch390_read_reg(CH390_EPCR) & 0x01u) != 0u)
-    {
-        if (poll_count == 0u)
-        {
-            ch390_write_reg(CH390_EPCR, 0x00u);
-            return -1;
-        }
-        --poll_count;
-    }
-
-    return 0;
-}
-
-void ch390_probe_rx_header(uint8_t *head)
-{
-    if (head == 0)
-    {
-        return;
-    }
-
-    ch390_read_mem(head, 4);
-}
-
-int ch390_peek_packet(uint8_t *rx_status, uint16_t *rx_len)
-{
-    uint8_t nsr;
-    uint8_t header[4];
-    uint16_t mrr;
-
-    if (rx_status != 0)
-    {
-        *rx_status = 0u;
-    }
-
-    if (rx_len != 0)
-    {
-        *rx_len = 0u;
-    }
-
-    nsr = ch390_read_reg(CH390_NSR);
-    if ((nsr & NSR_RXRDY) == 0u)
-    {
-        return 0;
-    }
-
-    mrr = (uint16_t)ch390_read_mrrl() | ((uint16_t)ch390_read_mrrh() << 8);
-    ch390_read_mem(header, 4);
-    ch390_write_reg(CH390_MRRL, (uint8_t)(mrr & 0xffu));
-    ch390_write_reg(CH390_MRRH, (uint8_t)((mrr >> 8) & 0xffu));
-
-    if (rx_status != 0)
-    {
-        *rx_status = header[1];
-    }
-
-    if (rx_len != 0)
-    {
-        *rx_len = (uint16_t)header[2] | ((uint16_t)header[3] << 8);
-    }
-
-    return 1;
-}
 
 /**
  * @name ch390_receive_packet
@@ -91,54 +24,46 @@ int ch390_peek_packet(uint8_t *rx_status, uint16_t *rx_len)
  */
 uint32_t ch390_receive_packet(uint8_t *buff, uint8_t *rx_status)
 {
-    uint8_t nsr;
+    uint8_t rx_ready;
-    uint8_t ready;
     uint16_t rx_len = 0;
 	uint8_t ReceiveData[4];
 
-    if (rx_status != 0)
+    // Check packet ready or not
-    {
+    ch390_read_reg(CH390_MRCMDX);
-        *rx_status = 0u;
+    rx_ready = ch390_read_reg(CH390_MRCMDX);
-    }
 
-    nsr = ch390_read_reg(CH390_NSR);
+    // if rxbyte != 1 or 0 reset pointer
-
+    if (rx_ready & CH390_PKT_ERR)
-    if ((nsr & NSR_RXRDY) == 0u)
     {
+        // Reset RX FIFO pointer
+        uint8_t rcr = ch390_read_reg(CH390_RCR);
+        ch390_write_reg(CH390_RCR, rcr & ~RCR_RXEN); //RX disable
+        ch390_write_reg(CH390_MPTRCR, 0x01);  //Reset RX FIFO pointer
+        ch390_write_reg(CH390_MRRH, 0x0c);
+        ch390_delay_us(1000);
+        ch390_write_reg(CH390_RCR, rcr | RCR_RXEN); //RX Enable
         return 0;
     }
-
+    if (!(rx_ready & CH390_PKT_RDY))
-    (void)ch390_read_mrcmdx();
-    ready = ch390_read_mrcmdx1();
-    if (ready == 0u)
     {
         return 0;
     }
-    if (ready != CH390_PKT_RDY)
-    {
-        ch390_rx_reset();
-        return 0;
-    }
 
     ch390_read_mem(ReceiveData, 4);
 
-    if (rx_status != 0)
-    {
     *rx_status = ReceiveData[1];
-    }
+    rx_len = ReceiveData[2] | (ReceiveData[3] << 8);
-    rx_len = (uint16_t)ReceiveData[2] | ((uint16_t)ReceiveData[3] << 8);
 
-    if ((ReceiveData[0] != CH390_PKT_RDY) ||
+    if(rx_len <= CH390_PKT_MAX)
-        ((ReceiveData[1] & 0x3Fu) != 0u) ||
+    {
-        (rx_len < (uint16_t)(14u + CH390_PKT_CRC_LEN)) ||
+        ch390_read_mem(buff, rx_len);
-        (rx_len > CH390_PKT_MAX))
+    }
+
+    if ((*rx_status & 0x3f) || (rx_len > CH390_PKT_MAX))
     {
-        ch390_rx_reset();
         return 0;
     }
-
+    return rx_len;
-    ch390_read_mem(buff, rx_len);
-    return (uint32_t)(rx_len - CH390_PKT_CRC_LEN);
 }
 
 /**
@@ -147,27 +72,17 @@ uint32_t ch390_receive_packet(uint8_t *buff, uint8_t *rx_status)
  * @param buff - Data to be sent
  * @param length - Less than 3k bytes.
  */
-int ch390_send_packet(uint8_t *buff, uint16_t length)
+void ch390_send_packet(uint8_t *buff, uint16_t length)
 {
-    uint32_t spin_count = 0u;
-
     // Write data to SRAM
     ch390_write_mem(buff, length);
     // Wait until last transmit complete
-    while ((ch390_read_reg(CH390_TCR) & TCR_TXREQ) != 0u)
+    while(ch390_read_reg(CH390_TCR) & TCR_TXREQ);
-    {
-        ++spin_count;
-        if (spin_count >= 4096u)
-        {
-            return -1;
-        }
-    }
     // Set current packet length
     ch390_write_reg(CH390_TXPLL, length & 0xff);
     ch390_write_reg(CH390_TXPLH, (length >> 8) & 0xff);
     // Issue transmit request
     ch390_send_request();
-    return 0;
 }
 
 /**
@@ -188,7 +103,7 @@ void ch390_send_request()
  */
 void ch390_drop_packet(uint16_t len)
 {
-    uint16_t mdr = (uint16_t)ch390_read_mrrl() | ((uint16_t)ch390_read_mrrh() << 8);
+    uint16_t mdr = ch390_read_reg(CH390_MRRL) | (ch390_read_reg(CH390_MRRH) << 8);
 #ifdef CH390_INTERFACE_16_BIT
     mdr = mdr + (len + 1) / 2 * 2;
 #else
@@ -199,17 +114,6 @@ void ch390_drop_packet(uint16_t len)
     ch390_write_reg(CH390_MRRH, (mdr >> 8) & 0xff);
 }
 
-void ch390_rx_reset(void)
-{
-    uint8_t rcr = ch390_read_reg(CH390_RCR);
-
-    ch390_write_reg(CH390_RCR, (uint8_t)(rcr & (uint8_t)(~RCR_RXEN)));
-    ch390_write_reg(CH390_MPTRCR, MPTRCR_RST_RX);
-    ch390_write_reg(CH390_NSR, NSR_RXOV);
-    ch390_write_reg(CH390_ISR, (uint8_t)(ISR_ROS | ISR_ROO | ISR_PR));
-    ch390_write_reg(CH390_RCR, (uint8_t)(rcr | RCR_RXEN));
-}
-
 /**
  * @name ch390_read_phy
  * @brief Read PHY register
@@ -217,12 +121,16 @@ void ch390_rx_reset(void)
  */
 uint16_t ch390_read_phy(uint8_t reg)
 {
+    uint32_t timeout = CH390_PHY_BUSY_TIMEOUT_LOOPS;
+
     ch390_write_reg(CH390_EPAR, CH390_PHY | reg);
     // Chose PHY, send read command
     ch390_write_reg(CH390_EPCR, EPCR_ERPRR | EPCR_EPOS);
-    if (ch390_wait_epcr_ready() != 0)
+    while ((ch390_read_reg(CH390_EPCR) & EPCR_ERRE) != 0u) {
-    {
+        if (timeout-- == 0u) {
-        return 0xFFFFu;
+            ch390_write_reg(CH390_EPCR, 0x00);
+            return 0;
+        }
     }
     // Clear read command
     ch390_write_reg(CH390_EPCR, 0x00);
@@ -238,15 +146,19 @@ uint16_t ch390_read_phy(uint8_t reg)
  */
 void ch390_write_phy(uint8_t reg, uint16_t value)
 {
+    uint32_t timeout = CH390_PHY_BUSY_TIMEOUT_LOOPS;
+
     ch390_write_reg(CH390_EPAR, CH390_PHY | reg);
     ch390_write_reg(CH390_EPDRL, (value & 0xff));        // Low byte
     ch390_write_reg(CH390_EPDRH, ((value >> 8) & 0xff)); // High byte
     // Chose PHY, send write command
     ch390_write_reg(CH390_EPCR, 0x0A);
-    if (ch390_wait_epcr_ready() != 0)
+    while ((ch390_read_reg(CH390_EPCR) & EPCR_ERRE) != 0u) {
-    {
+        if (timeout-- == 0u) {
+            ch390_write_reg(CH390_EPCR, 0x00);
             return;
         }
+    }
     // Clear write command
     ch390_write_reg(CH390_EPCR, 0x00);
 }
@@ -264,10 +176,7 @@ void ch390_write_eeprom(uint8_t reg, uint16_t value)
     ch390_write_reg(CH390_EPDRH, ((value >> 8) & 0xff)); // High byte
     // Chose EEPROM, send write command
     ch390_write_reg(CH390_EPCR, EPCR_ERPRW);
-    if (ch390_wait_epcr_ready() != 0)
+    while(ch390_read_reg(CH390_EPCR) & 0x01);
-    {
-        return;
-    }
     // Clear write command
     ch390_write_reg(CH390_EPCR, 0x00);
 }
@@ -298,24 +207,22 @@ void ch390_default_config()
     // CH390 has built-in MAC, this is not necessary
     // uint8_t mac_addr[6] = { 0x50, 0x54, 0x7B, 0x84, 0x00, 0x73 };
     // Multicast address hash table
-    uint8_t multicase_addr[8] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+    uint8_t multicase_addr[8] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
 
     ch390_set_phy_mode(CH390_AUTO);
+    ch390_write_reg(CH390_INTCR, (uint8_t)(INCR_TYPE_OD | INCR_POL_L));
     // Clear status
     ch390_write_reg(CH390_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
     ch390_write_reg(CH390_ISR, 0xFF);         // Clear interrupt status
-    ch390_write_reg(CH390_INTCR, (uint8_t)(INCR_TYPE_OD | INCR_POL_L));
     ch390_write_reg(CH390_TCR2, 0x80);        // LED mode 1
     ch390_write_reg(CH390_TCSCR, TCSCR_ALL);  // Enable check sum generation
 
     // ch390_set_mac_address(mac_addr);
     ch390_set_multicast(multicase_addr);
-    ch390_write_reg(CH390_BCASTCR, 0x00);
-    ch390_write_reg(CH390_MAR + 7, 0x80);
 
-    // Keep pointer auto-return enabled to stay aligned with the reference behavior.
+    // Enable only the interrupts needed by the NO_SYS polling path.
-    ch390_write_reg(CH390_IMR, (uint8_t)(IMR_PAR | IMR_PRI | IMR_LNKCHGI | IMR_ROOI | IMR_ROI));
+    ch390_write_reg(CH390_IMR, (uint8_t)(IMR_PRI | IMR_LNKCHGI | IMR_ROOI | IMR_ROI));
-    // Enable RX
+    // Enable RX with the reference receive filter.
     ch390_write_reg(CH390_RCR, RCR_DIS_CRC | RCR_RXEN);
 }
 
@@ -723,44 +630,3 @@ uint8_t ch390_get_int_status()
     ch390_write_reg(CH390_ISR, int_status);
     return int_status;
 }
-
-uint8_t ch390_runtime_poll(struct ch390_runtime_status *status)
-{
-    uint8_t int_status = ch390_read_reg(CH390_ISR);
-
-    if (status != 0)
-    {
-        status->int_status = int_status;
-        status->nsr = ch390_read_reg(CH390_NSR);
-        status->bcastcr = ch390_read_reg(CH390_BCASTCR);
-        status->mar7 = ch390_read_reg(CH390_MAR + 7u);
-        status->mrcmdx = 0u;
-        status->mrcmdx1 = 0u;
-        status->mrrl = 0u;
-        status->mrrh = 0u;
-        status->link_up = ((status->nsr & NSR_LINKST) != 0u) ? 1u : 0u;
-    }
-
-    ch390_write_reg(CH390_ISR, int_status);
-    return int_status;
-}
-
-int ch390_runtime_link_up_from_status(const struct ch390_runtime_status *status)
-{
-    if (status == 0)
-    {
-        return 0;
-    }
-
-    return (status->link_up != 0u) ? 1 : 0;
-}
-
-uint32_t ch390_runtime_receive_packet(uint8_t *buff, uint8_t *rx_status)
-{
-    return ch390_receive_packet(buff, rx_status);
-}
-
-int ch390_runtime_send_packet(uint8_t *buff, uint16_t length)
-{
-    return ch390_send_packet(buff, length);
-}

Drivers/CH390/CH390.h

@@ -150,8 +150,6 @@ enum ch390_phy_mode
 #define CH390_BCASTCR   0x53
 #define CH390_INTCKCR   0x54
 #define CH390_MPTRCR    0x55
-    #define MPTRCR_RST_TX   (1<<1)
-    #define MPTRCR_RST_RX   (1<<0)
 #define CH390_MLEDCR    0x57
 #define CH390_MRCMDX    0x70
 #define CH390_MRCMDX1   0x71
@@ -304,8 +302,6 @@ enum ch390_phy_mode
 #define CH390_RLENCR    0x52
 #define CH390_BCASTCR   0x53
 #define CH390_MPTRCR    0x55
-    #define MPTRCR_RST_TX   (1<<1)
-    #define MPTRCR_RST_RX   (1<<0)
 #define CH390_MRCMDX    0xF0
 #define CH390_MRCMDX1   0xF1
 #define CH390_MRCMD     0xF2
@@ -360,23 +356,9 @@ enum ch390_phy_mode
 #define CH390_PKT_NONE  0x00    /* No packet received */
 #define CH390_PKT_RDY   0x01    /* Packet ready to receive */
 #define CH390_PKT_ERR   0xFE    /* Un-stable states */
-#define CH390_PKT_CRC_LEN 4u    /* Ethernet FCS stored in RX SRAM */
 #define CH390_PKT_MAX   1536    /* Received packet max size */
 #define CH390_PKT_MIN   64
 
-struct ch390_runtime_status
-{
-    uint8_t int_status;
-    uint8_t nsr;
-    uint8_t bcastcr;
-    uint8_t mar7;
-    uint8_t mrcmdx;
-    uint8_t mrcmdx1;
-    uint8_t mrrl;
-    uint8_t mrrh;
-    uint8_t link_up;
-};
-
 /********************************************************************
  * Functions
  */
@@ -397,7 +379,7 @@ uint32_t ch390_receive_packet(uint8_t *buff, uint8_t *rx_status);
  * @param buff - Data to be sent
  * @param length - Less than 3k bytes.
  */
-int ch390_send_packet(uint8_t *buff, uint16_t length);
+void ch390_send_packet(uint8_t *buff, uint16_t length);
 
 /**
  * @name ch390_send_request
@@ -638,60 +620,4 @@ void ch390_int_pin_config(uint8_t type, uint8_t pol);
  */
 uint8_t ch390_get_int_status(void);
 
-/**
- * @name ch390_runtime_poll
- * @brief Poll runtime state, sample diagnostic registers, and clear ISR flags.
- * @param status - Output runtime status snapshot
- * @return Interrupt status snapshot
- */
-uint8_t ch390_runtime_poll(struct ch390_runtime_status *status);
-
-/**
- * @name ch390_runtime_link_up_from_status
- * @brief Get link state from a runtime status snapshot
- * @param status - Runtime status snapshot
- * @return 0: Link down  1: Link up
- */
-int ch390_runtime_link_up_from_status(const struct ch390_runtime_status *status);
-
-/**
- * @name ch390_probe_rx_header
- * @brief Diagnostic helper: read 4-byte RX header directly from RX SRAM.
- *        Caller must restore MRR if a non-destructive probe is required.
- * @param head - Output buffer with at least 4 bytes.
- */
-void ch390_probe_rx_header(uint8_t *head);
-
-/**
- * @name ch390_peek_packet
- * @brief Peek current RX header without consuming the packet.
- * @param rx_status - Output abnormal status while receiving packet
- * @param rx_len - Output packet length from RX header
- * @return 0: no packet pending  1: header sampled
- */
-int ch390_peek_packet(uint8_t *rx_status, uint16_t *rx_len);
-
-/**
- * @name ch390_rx_reset
- * @brief Repair RX datapath after overflow/corruption without full chip reset.
- */
-void ch390_rx_reset(void);
-
-/**
- * @name ch390_runtime_receive_packet
- * @brief Runtime RX entry point for packet receive
- * @param buff - Size equal to CH390_PKT_MAX
- * @param rx_status - Output abnormal status while receiving packet
- * @return Packet length
- */
-uint32_t ch390_runtime_receive_packet(uint8_t *buff, uint8_t *rx_status);
-
-/**
- * @name ch390_runtime_send_packet
- * @brief Runtime TX entry point for packet transmit
- * @param buff - Data to be sent
- * @param length - Less than 3k bytes.
- */
-int ch390_runtime_send_packet(uint8_t *buff, uint16_t length);
-
 #endif /* __CH390_H */

Drivers/CH390/CH390_Interface.c

@@ -15,6 +15,7 @@
 #include "main.h"
 #include "CH390.h"
 #include "CH390_Interface.h"
+#include "SEGGER_RTT.h"
 
 /* FreeRTOS includes */
 #ifdef USE_FREERTOS
@@ -47,6 +48,13 @@
 #define CH390_INT_PORT      GPIOB
 #define CH390_INT_PIN       GPIO_PIN_0
 
+#define CH390_SCK_PORT      GPIOA
+#define CH390_SCK_PIN       GPIO_PIN_5
+#define CH390_MISO_PORT     GPIOA
+#define CH390_MISO_PIN      GPIO_PIN_6
+#define CH390_MOSI_PORT     GPIOA
+#define CH390_MOSI_PIN      GPIO_PIN_7
+
 /* External SPI handle from spi.c */
 extern SPI_HandleTypeDef hspi1;
 
@@ -54,14 +62,6 @@ extern SPI_HandleTypeDef hspi1;
 #define SPI_TIMEOUT         100
 #define CH390_SPI_CHUNK_SIZE 64u
 
-#ifdef USE_FREERTOS
-#define CH390_SPI_ATOMIC_ENTER()  taskENTER_CRITICAL()
-#define CH390_SPI_ATOMIC_EXIT()   taskEXIT_CRITICAL()
-#else
-#define CH390_SPI_ATOMIC_ENTER()  ((void)0)
-#define CH390_SPI_ATOMIC_EXIT()   ((void)0)
-#endif
-
 /*----------------------------------------------------------------------------
  * Low-level GPIO operations
  *---------------------------------------------------------------------------*/
@@ -129,7 +129,6 @@ static void ch390_spi_apply_mode(uint32_t polarity, uint32_t phase)
     hspi1.Init.CLKPolarity = polarity;
     hspi1.Init.CLKPhase = phase;
     hspi1.Init.NSS = SPI_NSS_SOFT;
-
     if (HAL_SPI_Init(&hspi1) != HAL_OK)
     {
         Error_Handler();
@@ -188,8 +187,6 @@ void ch390_interrupt_init(void)
     /* EXTI0 is configured in CubeMX for PB0 */
     /* NVIC priority should be >= configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY */
     /* for FreeRTOS compatibility */
-    HAL_NVIC_DisableIRQ(EXTI0_IRQn);
-    __HAL_GPIO_EXTI_CLEAR_IT(CH390_INT_PIN);
     HAL_NVIC_SetPriority(EXTI0_IRQn, 6, 0);
     HAL_NVIC_EnableIRQ(EXTI0_IRQn);
 }
@@ -201,8 +198,10 @@ void ch390_interrupt_init(void)
  */
 void ch390_spi_init(void)
 {
+    /* SPI1 is initialized by MX_SPI1_Init() in main.c */
     /* Reference CH390 SPI path uses mode 3. */
     ch390_spi_apply_mode(SPI_POLARITY_HIGH, SPI_PHASE_2EDGE);
+    SEGGER_RTT_WriteString(0, "CH390 SPI mode=3 (CPOL=1 CPHA=1)\r\n");
 }
 
 /**
@@ -273,50 +272,14 @@ uint8_t ch390_read_reg(uint8_t reg)
 {
     uint8_t value;
     
-    CH390_SPI_ATOMIC_ENTER();
     ch390_cs(0);                                /* CS low - select */
     ch390_spi_exchange_byte(reg | OPC_REG_R);   /* Send read command */
     value = ch390_spi_dummy_read();             /* Read register value */
     ch390_cs(1);                                /* CS high - deselect */
-    CH390_SPI_ATOMIC_EXIT();
     
     return value;
 }
 
-static uint8_t ch390_read_rx_reg(uint8_t reg)
-{
-    uint8_t value;
-
-    CH390_SPI_ATOMIC_ENTER();
-    ch390_cs(0);
-    ch390_spi_exchange_byte(reg | OPC_REG_R);
-    value = ch390_spi_dummy_read();
-    ch390_cs(1);
-    CH390_SPI_ATOMIC_EXIT();
-
-    return value;
-}
-
-uint8_t ch390_read_mrcmdx(void)
-{
-    return ch390_read_rx_reg(CH390_MRCMDX);
-}
-
-uint8_t ch390_read_mrcmdx1(void)
-{
-    return ch390_read_rx_reg(CH390_MRCMDX1);
-}
-
-uint8_t ch390_read_mrrl(void)
-{
-    return ch390_read_rx_reg(CH390_MRRL);
-}
-
-uint8_t ch390_read_mrrh(void)
-{
-    return ch390_read_rx_reg(CH390_MRRH);
-}
-
 /**
  * @brief Write a CH390 register
  * @param reg Register address
@@ -324,12 +287,10 @@ uint8_t ch390_read_mrrh(void)
  */
 void ch390_write_reg(uint8_t reg, uint8_t value)
 {
-    CH390_SPI_ATOMIC_ENTER();
     ch390_cs(0);                                /* CS low - select */
-    ch390_spi_exchange_byte(reg | OPC_REG_W);   /* Send write command */
+    (void)ch390_spi_exchange_byte(reg | OPC_REG_W);
-    ch390_spi_exchange_byte(value);             /* Write register value */
+    (void)ch390_spi_exchange_byte(value);
     ch390_cs(1);                                /* CS high - deselect */
-    CH390_SPI_ATOMIC_EXIT();
 }
 
 /**
@@ -339,19 +300,17 @@ void ch390_write_reg(uint8_t reg, uint8_t value)
  */
 void ch390_read_mem(uint8_t *data, int length)
 {
-    if ((data == NULL) || (length <= 0))
+    if (data == NULL || length <= 0)
     {
         return;
     }
 
-    CH390_SPI_ATOMIC_ENTER();
     ch390_cs(0);                                /* CS low - select */
     ch390_spi_exchange_byte(OPC_MEM_READ);      /* Send memory read command */
 
     (void)ch390_spi_read_bytes(data, (uint16_t)length);
     
     ch390_cs(1);                                /* CS high - deselect */
-    CH390_SPI_ATOMIC_EXIT();
 }
 
 /**
@@ -381,24 +340,17 @@ void ch390_read_mem_dma(uint8_t *data, int length)
  */
 void ch390_write_mem(uint8_t *data, int length)
 {
-    int i;
+    if (data == NULL || length <= 0)
-
-    if ((data == NULL) || (length <= 0))
     {
         return;
     }
 
-    CH390_SPI_ATOMIC_ENTER();
     ch390_cs(0);                                /* CS low - select */
     ch390_spi_exchange_byte(OPC_MEM_WRITE);     /* Send memory write command */
 
-    for (i = 0; i < length; ++i)
+    (void)HAL_SPI_Transmit(&hspi1, data, (uint16_t)length, SPI_TIMEOUT);
-    {
-        (void)ch390_spi_exchange_byte(data[i]);
-    }
     
     ch390_cs(1);                                /* CS high - deselect */
-    CH390_SPI_ATOMIC_EXIT();
 }
 
 /**

Drivers/CH390/CH390_Interface.h

@@ -28,34 +28,6 @@ void ch390_hardware_reset(void);
  */
 uint8_t ch390_read_reg(uint8_t reg);
 
-/**
- * @name ch390_read_mrcmdx
- * @brief Read MRCMDX receive-ready latch
- * @return Register value
- */
-uint8_t ch390_read_mrcmdx(void);
-
-/**
- * @name ch390_read_mrcmdx1
- * @brief Read MRCMDX1 receive-ready latch
- * @return Register value
- */
-uint8_t ch390_read_mrcmdx1(void);
-
-/**
- * @name ch390_read_mrrl
- * @brief Read MRRL receive memory pointer register
- * @return Register value
- */
-uint8_t ch390_read_mrrl(void);
-
-/**
- * @name ch390_read_mrrh
- * @brief Read MRRH receive memory pointer register
- * @return Register value
- */
-uint8_t ch390_read_mrrh(void);
-
 /**
  * @name ch390_write_reg
  * @brief Write register

Drivers/CH390/ch390_runtime.c

@@ -0,0 +1,379 @@
+#include "ch390_runtime.h"
+
+#include "CH390.h"
+#include "CH390_Interface.h"
+#include "SEGGER_RTT.h"
+#include "ethernetif.h"
+#include "stm32f1xx_hal.h"
+#include "lwip/etharp.h"
+#include "lwip/pbuf.h"
+#include "lwip/stats.h"
+
+#include <string.h>
+
+static void ch390_runtime_dispatch_frame(struct netif *netif, struct pbuf *p)
+{
+    if ((p != NULL) && (netif->input(p, netif) != ERR_OK)) {
+        pbuf_free(p);
+    }
+}
+
+static uint8_t ch390_runtime_drain_rx(struct netif *netif, uint8_t max_frames)
+{
+    struct pbuf *p;
+    uint8_t drained = 0u;
+
+    while (drained < max_frames) {
+        p = ch390_runtime_input_frame(netif);
+        if (p == NULL) {
+            break;
+        }
+        ch390_runtime_dispatch_frame(netif, p);
+        drained++;
+    }
+
+    return drained;
+}
+
+static volatile uint8_t g_ch390_irq_pending;
+static uint8_t g_ch390_ready;
+static ch390_diag_t g_diag;
+
+static uint8_t ch390_runtime_probe_identity(void)
+{
+    g_diag.vendor_id = ch390_get_vendor_id();
+    g_diag.product_id = ch390_get_product_id();
+    g_diag.revision = ch390_get_revision();
+    g_diag.phy_bmcr = ch390_read_phy(CH390_PHY_BMCR);
+    g_diag.phy_bmsr = ch390_read_phy(CH390_PHY_BMSR);
+    g_diag.phy_id1 = ch390_read_phy(CH390_PHY_PHYID1);
+    g_diag.phy_id2 = ch390_read_phy(CH390_PHY_PHYID2);
+    g_diag.phy_anar = ch390_read_phy(CH390_PHY_ANAR);
+    g_diag.phy_anlpar = ch390_read_phy(CH390_PHY_ANLPAR);
+    g_diag.phy_aner = ch390_read_phy(CH390_PHY_ANER);
+    g_diag.nsr = ch390_read_reg(CH390_NSR);
+    g_diag.ncr = ch390_read_reg(CH390_NCR);
+    g_diag.rcr = ch390_read_reg(CH390_RCR);
+    g_diag.imr = ch390_read_reg(CH390_IMR);
+    g_diag.intcr = ch390_read_reg(CH390_INTCR);
+    g_diag.gpr = ch390_read_reg(CH390_GPR);
+    g_diag.isr = ch390_read_reg(CH390_ISR);
+    g_diag.phy_speed_10m = 0u;
+    g_diag.phy_full_duplex = 0u;
+    g_diag.link_up = (uint8_t)0u;
+    g_diag.id_valid = (uint8_t)((g_diag.vendor_id != 0x0000u) &&
+                                (g_diag.vendor_id != 0xFFFFu) &&
+                                (g_diag.product_id != 0x0000u) &&
+                                (g_diag.product_id != 0xFFFFu));
+    return g_diag.id_valid;
+}
+
+static void ch390_runtime_refresh_diag(void)
+{
+    uint8_t id_valid = ch390_runtime_probe_identity();
+    g_diag.int_pin = (uint8_t)ch390_get_int_pin();
+
+    if (id_valid != 0u) {
+        g_diag.phy_speed_10m = (uint8_t)ch390_get_phy_speed();
+        g_diag.phy_full_duplex = (uint8_t)ch390_get_duplex_mode();
+        g_diag.link_up = (uint8_t)ch390_get_link_status();
+    }
+}
+
+struct pbuf *ch390_runtime_input_frame(struct netif *netif)
+{
+    struct ethernetif *ethernetif = (struct ethernetif *)netif->state;
+    struct pbuf *p = NULL;
+    struct pbuf *q;
+    uint16_t len;
+    uint16_t frame_len;
+    uint8_t rcr;
+    uint8_t rx_ready;
+    uint8_t rx_header[4];
+    ch390_read_reg(CH390_MRCMDX);
+    rx_ready = ch390_read_reg(CH390_MRCMDX);
+
+    if (rx_ready & CH390_PKT_ERR) {
+        rcr = ch390_read_reg(CH390_RCR);
+        ch390_write_reg(CH390_RCR, (uint8_t)(rcr & (uint8_t)(~RCR_RXEN)));
+        ch390_write_reg(CH390_MPTRCR, 0x01u);
+        ch390_write_reg(CH390_MRRH, 0x0Cu);
+        ch390_delay_us(1000u);
+        ch390_write_reg(CH390_RCR, rcr);
+        ethernetif->rx_len = 0u;
+        LINK_STATS_INC(link.drop);
+        g_diag.rx_packets_drop++;
+        return NULL;
+    }
+
+    if ((rx_ready & CH390_PKT_RDY) == 0u) {
+        ethernetif->rx_len = 0u;
+        return NULL;
+    }
+
+    g_diag.rx_ready_hits++;
+
+    ch390_read_mem(rx_header, 4);
+    ethernetif->rx_status = rx_header[1];
+    frame_len = (uint16_t)((uint16_t)rx_header[2] | ((uint16_t)rx_header[3] << 8));
+
+    if ((ethernetif->rx_status & 0x3Fu) != 0u || frame_len == 0u || frame_len > CH390_PKT_MAX) {
+        ethernetif->rx_len = 0u;
+        ch390_drop_packet(frame_len);
+        LINK_STATS_INC(link.drop);
+        g_diag.rx_packets_drop++;
+        return NULL;
+    }
+
+    ethernetif->rx_len = frame_len;
+    len = ethernetif->rx_len;
+#if ETH_PAD_SIZE
+    len += ETH_PAD_SIZE;
+#endif
+
+    p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+    if (p != NULL) {
+#if ETH_PAD_SIZE
+        pbuf_remove_header(p, ETH_PAD_SIZE);
+#endif
+        for (q = p; q != NULL; q = q->next) {
+            ch390_read_mem((uint8_t *)q->payload, q->len);
+        }
+#if ETH_PAD_SIZE
+        pbuf_add_header(p, ETH_PAD_SIZE);
+#endif
+        LINK_STATS_INC(link.recv);
+        g_diag.rx_packets_ok++;
+
+        g_diag.last_frame_len = frame_len;
+        g_diag.last_payload_len = p->tot_len;
+    } else {
+        ch390_drop_packet(ethernetif->rx_len);
+        LINK_STATS_INC(link.memerr);
+        LINK_STATS_INC(link.drop);
+        g_diag.rx_packets_drop++;
+    }
+
+    return p;
+}
+
+bool ch390_mac_address_valid(const uint8_t *mac)
+{
+    if (mac == NULL) {
+        return false;
+    }
+    for (uint8_t i = 0; i < ETHARP_HWADDR_LEN; ++i) {
+        if (mac[i] == 0u) {
+            return false;
+        }
+    }
+    return true;
+}
+
+void ch390_runtime_init(struct netif *netif, const uint8_t *mac)
+{
+    struct ethernetif *ethernetif = (struct ethernetif *)netif->state;
+
+    SEGGER_RTT_WriteString(0, "ETH init: gpio\r\n");
+    ch390_gpio_init();
+    SEGGER_RTT_WriteString(0, "ETH init: spi\r\n");
+    ch390_spi_init();
+    SEGGER_RTT_WriteString(0, "ETH init: reset\r\n");
+    ch390_hardware_reset();
+
+    SEGGER_RTT_WriteString(0, "ETH init: probe\r\n");
+    g_ch390_ready = ch390_runtime_probe_identity();
+    if (g_ch390_ready == 0u) {
+        netif->hwaddr_len = ETHARP_HWADDR_LEN;
+        netif->mtu = 1500;
+        netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET;
+
+        ethernetif->rx_len = 0u;
+        ethernetif->rx_status = 0u;
+
+        netif_set_link_down(netif);
+        SEGGER_RTT_WriteString(0, "ETH init: invalid chip id\r\n");
+        return;
+    }
+
+    SEGGER_RTT_WriteString(0, "ETH init: default\r\n");
+    ch390_default_config();
+    SEGGER_RTT_WriteString(0, "ETH init: mac\r\n");
+    if (ch390_mac_address_valid(mac)) {
+        ch390_set_mac_address((uint8_t *)mac);
+    }
+    else {
+        if (mac != NULL) {
+            ch390_get_mac((uint8_t *)mac);
+            SEGGER_RTT_printf(0, "ETH init: invalid MAC in config, using hardware MAC: %02X:%02X:%02X:%02X:%02X:%02X\r\n",
+                                  mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+        }
+        else {
+            SEGGER_RTT_WriteString(0, "ETH init: no MAC in config\r\n");
+        }
+    }
+
+    netif->hwaddr_len = ETHARP_HWADDR_LEN;
+    SEGGER_RTT_WriteString(0, "ETH init: getmac\r\n");
+    ch390_get_mac(netif->hwaddr);
+    netif->mtu = 1500;
+    netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET;
+
+    ethernetif->rx_len = 0u;
+    ethernetif->rx_status = 0u;
+
+    ch390_runtime_refresh_diag();
+    g_ch390_ready = g_diag.id_valid;
+
+    SEGGER_RTT_WriteString(0, "ETH init: irq\r\n");
+    ch390_interrupt_init();
+    SEGGER_RTT_WriteString(0, "ETH init: done\r\n");
+}
+
+void ch390_runtime_set_irq_pending(void)
+{
+    g_ch390_irq_pending = 1u;
+}
+
+uint8_t ch390_runtime_is_irq_pending(void)
+{
+    return g_ch390_irq_pending;
+}
+
+void ch390_runtime_poll(struct netif *netif)
+{
+    uint8_t int_status;
+    uint8_t rx_ready;
+    uint8_t rx_budget;
+    uint8_t rx_hint;
+
+    if (!g_ch390_ready) {
+        return;
+    }
+
+    g_diag.rx_poll_calls++;
+
+    rx_budget = 1u;
+    rx_hint = 0u;
+
+    if ((g_ch390_irq_pending != 0u) || (ch390_get_int_pin() == GPIO_PIN_RESET)) {
+        g_ch390_irq_pending = 0u;
+        int_status = ch390_get_int_status();
+
+        if ((int_status & ISR_LNKCHG) != 0u) {
+            ch390_runtime_check_link(netif);
+        }
+
+        if ((int_status & ISR_ROS) != 0u) {
+            LINK_STATS_INC(link.err);
+        }
+
+        if ((int_status & (ISR_PR | ISR_ROS | ISR_ROO)) != 0u) {
+            rx_hint = 1u;
+            rx_budget = 8u;
+        }
+    }
+
+    ch390_read_reg(CH390_MRCMDX);
+    rx_ready = ch390_read_reg(CH390_MRCMDX);
+    if ((rx_ready & CH390_PKT_RDY) != 0u) {
+        rx_hint = 1u;
+        if (rx_budget < 4u) {
+            rx_budget = 4u;
+        }
+    }
+
+    if (rx_hint != 0u) {
+        (void)ch390_runtime_drain_rx(netif, rx_budget);
+    }
+}
+
+void ch390_runtime_check_link(struct netif *netif)
+{
+    uint8_t link_up;
+    static uint8_t s_last_reported = 0xFFu;
+
+    if (!g_ch390_ready) {
+        netif_set_link_down(netif);
+        return;
+    }
+
+    ch390_runtime_refresh_diag();
+    link_up = (uint8_t)ch390_get_link_status();
+
+    if (link_up != s_last_reported) {
+        SEGGER_RTT_printf(0,
+                          "ETH link %s nsr=0x%02X bmsr=0x%04X anlpar=0x%04X\r\n",
+                          link_up ? "up" : "down",
+                          g_diag.nsr,
+                          g_diag.phy_bmsr,
+                          g_diag.phy_anlpar);
+        s_last_reported = link_up;
+    }
+
+    if (link_up) {
+        if (!netif_is_link_up(netif)) {
+            netif_set_link_up(netif);
+        }
+    } else if (netif_is_link_up(netif)) {
+        netif_set_link_down(netif);
+    }
+}
+
+err_t ch390_runtime_output(struct netif *netif, struct pbuf *p)
+{
+    struct pbuf *q;
+    uint32_t start_tick;
+
+    LWIP_UNUSED_ARG(netif);
+
+    if (!g_ch390_ready) {
+        LINK_STATS_INC(link.drop);
+        return ERR_IF;
+    }
+
+#if ETH_PAD_SIZE
+    pbuf_remove_header(p, ETH_PAD_SIZE);
+#endif
+
+    start_tick = HAL_GetTick();
+    while (ch390_read_reg(CH390_TCR) & TCR_TXREQ) {
+        if ((HAL_GetTick() - start_tick) > 10u) {
+#if ETH_PAD_SIZE
+            pbuf_add_header(p, ETH_PAD_SIZE);
+#endif
+            LINK_STATS_INC(link.drop);
+            g_diag.tx_packets_timeout++;
+            return ERR_TIMEOUT;
+        }
+    }
+
+    for (q = p; q != NULL; q = q->next) {
+        ch390_write_mem((uint8_t *)q->payload, q->len);
+    }
+
+    ch390_write_reg(CH390_TXPLL, p->tot_len & 0xFFu);
+    ch390_write_reg(CH390_TXPLH, (p->tot_len >> 8) & 0xFFu);
+    ch390_send_request();
+
+#if ETH_PAD_SIZE
+    pbuf_add_header(p, ETH_PAD_SIZE);
+#endif
+
+    LINK_STATS_INC(link.xmit);
+    g_diag.tx_packets_ok++;
+    return ERR_OK;
+}
+
+void ch390_runtime_get_diag(ch390_diag_t *diag)
+{
+    if (diag != NULL) {
+        ch390_runtime_refresh_diag();
+        *diag = g_diag;
+    }
+}
+
+bool ch390_runtime_is_ready(void)
+{
+    return g_ch390_ready != 0u;
+}

Drivers/CH390/ch390_runtime.h

@@ -0,0 +1,62 @@
+#ifndef __CH390_RUNTIME_H__
+#define __CH390_RUNTIME_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "lwip/err.h"
+
+struct netif;
+struct pbuf;
+
+typedef struct {
+    uint16_t vendor_id;
+    uint16_t product_id;
+    uint8_t revision;
+    uint16_t phy_bmcr;
+    uint16_t phy_bmsr;
+    uint16_t phy_id1;
+    uint16_t phy_id2;
+    uint16_t phy_anar;
+    uint16_t phy_anlpar;
+    uint16_t phy_aner;
+    uint8_t nsr;
+    uint8_t ncr;
+    uint8_t rcr;
+    uint8_t imr;
+    uint8_t intcr;
+    uint8_t gpr;
+    uint8_t isr;
+    uint8_t int_pin;
+    uint8_t phy_speed_10m;
+    uint8_t phy_full_duplex;
+    uint8_t link_up;
+    uint8_t id_valid;
+    uint32_t rx_poll_calls;
+    uint32_t rx_ready_hits;
+    uint32_t rx_packets_ok;
+    uint32_t rx_packets_drop;
+    uint32_t tx_packets_ok;
+    uint32_t tx_packets_timeout;
+    uint32_t rx_arp_frames;
+    uint32_t rx_ip_frames;
+    uint32_t rx_other_frames;
+    uint32_t rx_unicast_self_frames;
+    uint32_t rx_broadcast_frames;
+    uint32_t rx_multicast_frames;
+    uint16_t last_frame_len;
+    uint16_t last_payload_len;
+    uint16_t last_eth_type;
+} ch390_diag_t;
+
+void ch390_runtime_init(struct netif *netif, const uint8_t *mac);
+struct pbuf *ch390_runtime_input_frame(struct netif *netif);
+void ch390_runtime_set_irq_pending(void);
+uint8_t ch390_runtime_is_irq_pending(void);
+void ch390_runtime_poll(struct netif *netif);
+void ch390_runtime_check_link(struct netif *netif);
+err_t ch390_runtime_output(struct netif *netif, struct pbuf *p);
+void ch390_runtime_get_diag(ch390_diag_t *diag);
+bool ch390_runtime_is_ready(void);
+
+#endif

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f100xb.s

@@ -1,313 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f100xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32F100xB Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                    ; Top of Stack
-                DCD     Reset_Handler                   ; Reset Handler
-                DCD     NMI_Handler                     ; NMI Handler
-                DCD     HardFault_Handler               ; Hard Fault Handler
-                DCD     MemManage_Handler               ; MPU Fault Handler
-                DCD     BusFault_Handler                ; Bus Fault Handler
-                DCD     UsageFault_Handler              ; Usage Fault Handler
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     SVC_Handler                     ; SVCall Handler
-                DCD     DebugMon_Handler                ; Debug Monitor Handler
-                DCD     0                               ; Reserved
-                DCD     PendSV_Handler                  ; PendSV Handler
-                DCD     SysTick_Handler                 ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                 ; Window Watchdog
-                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler               ; Tamper
-                DCD     RTC_IRQHandler                  ; RTC
-                DCD     FLASH_IRQHandler                ; Flash
-                DCD     RCC_IRQHandler                  ; RCC
-                DCD     EXTI0_IRQHandler                ; EXTI Line 0
-                DCD     EXTI1_IRQHandler                ; EXTI Line 1
-                DCD     EXTI2_IRQHandler                ; EXTI Line 2
-                DCD     EXTI3_IRQHandler                ; EXTI Line 3
-                DCD     EXTI4_IRQHandler                ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler                 ; ADC1
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
-                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
-                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
-                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
-                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler                 ; TIM2
-                DCD     TIM3_IRQHandler                 ; TIM3
-                DCD     TIM4_IRQHandler                 ; TIM4
-                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler              ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler              ; I2C2 Error
-                DCD     SPI1_IRQHandler                 ; SPI1
-                DCD     SPI2_IRQHandler                 ; SPI2
-                DCD     USART1_IRQHandler               ; USART1
-                DCD     USART2_IRQHandler               ; USART2
-                DCD     USART3_IRQHandler               ; USART3
-                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler             ; RTC Alarm through EXTI Line
-                DCD     CEC_IRQHandler                  ; HDMI-CEC
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved 
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved 
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
-                DCD     TIM7_IRQHandler                 ; TIM7
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                      [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler                [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler                [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler                 [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler               [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                      [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler                 [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                   [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                  [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                  [WEAK]
-                EXPORT  PVD_IRQHandler                   [WEAK]
-                EXPORT  TAMPER_IRQHandler                [WEAK]
-                EXPORT  RTC_IRQHandler                   [WEAK]
-                EXPORT  FLASH_IRQHandler                 [WEAK]
-                EXPORT  RCC_IRQHandler                   [WEAK]
-                EXPORT  EXTI0_IRQHandler                 [WEAK]
-                EXPORT  EXTI1_IRQHandler                 [WEAK]
-                EXPORT  EXTI2_IRQHandler                 [WEAK]
-                EXPORT  EXTI3_IRQHandler                 [WEAK]
-                EXPORT  EXTI4_IRQHandler                 [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
-                EXPORT  ADC1_IRQHandler                  [WEAK]
-                EXPORT  EXTI9_5_IRQHandler               [WEAK]
-                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler               [WEAK]
-                EXPORT  TIM2_IRQHandler                  [WEAK]
-                EXPORT  TIM3_IRQHandler                  [WEAK]
-                EXPORT  TIM4_IRQHandler                  [WEAK]
-                EXPORT  I2C1_EV_IRQHandler               [WEAK]
-                EXPORT  I2C1_ER_IRQHandler               [WEAK]
-                EXPORT  I2C2_EV_IRQHandler               [WEAK]
-                EXPORT  I2C2_ER_IRQHandler               [WEAK]
-                EXPORT  SPI1_IRQHandler                  [WEAK]
-                EXPORT  SPI2_IRQHandler                  [WEAK]
-                EXPORT  USART1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler                [WEAK]
-                EXPORT  USART3_IRQHandler                [WEAK]
-                EXPORT  EXTI15_10_IRQHandler             [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
-                EXPORT  CEC_IRQHandler                   [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
-                EXPORT  TIM7_IRQHandler                  [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM15_IRQHandler
-TIM1_UP_TIM16_IRQHandler
-TIM1_TRG_COM_TIM17_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-CEC_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f100xe.s

@@ -1,344 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f100xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32F100xE Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system and also configure the external 
-;*                        SRAM mounted on STM32100E-EVAL board to be used as data 
-;*                        memory (optional, to be enabled by user)
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                    ; Top of Stack
-                DCD     Reset_Handler                   ; Reset Handler
-                DCD     NMI_Handler                     ; NMI Handler
-                DCD     HardFault_Handler               ; Hard Fault Handler
-                DCD     MemManage_Handler               ; MPU Fault Handler
-                DCD     BusFault_Handler                ; Bus Fault Handler
-                DCD     UsageFault_Handler              ; Usage Fault Handler
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     SVC_Handler                     ; SVCall Handler
-                DCD     DebugMon_Handler                ; Debug Monitor Handler
-                DCD     0                               ; Reserved
-                DCD     PendSV_Handler                  ; PendSV Handler
-                DCD     SysTick_Handler                 ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                 ; Window Watchdog
-                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler               ; Tamper
-                DCD     RTC_IRQHandler                  ; RTC
-                DCD     FLASH_IRQHandler                ; Flash
-                DCD     RCC_IRQHandler                  ; RCC
-                DCD     EXTI0_IRQHandler                ; EXTI Line 0
-                DCD     EXTI1_IRQHandler                ; EXTI Line 1
-                DCD     EXTI2_IRQHandler                ; EXTI Line 2
-                DCD     EXTI3_IRQHandler                ; EXTI Line 3
-                DCD     EXTI4_IRQHandler                ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler                 ; ADC1
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
-                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
-                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
-                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
-                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler                 ; TIM2
-                DCD     TIM3_IRQHandler                 ; TIM3
-                DCD     TIM4_IRQHandler                 ; TIM4
-                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler              ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler              ; I2C2 Error
-                DCD     SPI1_IRQHandler                 ; SPI1
-                DCD     SPI2_IRQHandler                 ; SPI2
-                DCD     USART1_IRQHandler               ; USART1
-                DCD     USART2_IRQHandler               ; USART2
-                DCD     USART3_IRQHandler               ; USART3
-                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler             ; RTC Alarm through EXTI Line
-                DCD     CEC_IRQHandler                  ; HDMI CEC
-                DCD     TIM12_IRQHandler                ; TIM12
-                DCD     TIM13_IRQHandler                ; TIM13 
-                DCD     TIM14_IRQHandler                ; TIM14
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     0                               ; Reserved
-                DCD     TIM5_IRQHandler                 ; TIM5
-                DCD     SPI3_IRQHandler                 ; SPI3
-                DCD     UART4_IRQHandler                ; UART4
-                DCD     UART5_IRQHandler                ; UART5
-                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
-                DCD     TIM7_IRQHandler                 ; TIM7
-                DCD     DMA2_Channel1_IRQHandler        ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler        ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler        ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler      ; DMA2 Channel4 & Channel5
-                DCD     DMA2_Channel5_IRQHandler        ; DMA2 Channel5                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                      [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler                [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler                [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler                 [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler               [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                      [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler                 [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                   [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                  [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                  [WEAK]
-                EXPORT  PVD_IRQHandler                   [WEAK]
-                EXPORT  TAMPER_IRQHandler                [WEAK]
-                EXPORT  RTC_IRQHandler                   [WEAK]
-                EXPORT  FLASH_IRQHandler                 [WEAK]
-                EXPORT  RCC_IRQHandler                   [WEAK]
-                EXPORT  EXTI0_IRQHandler                 [WEAK]
-                EXPORT  EXTI1_IRQHandler                 [WEAK]
-                EXPORT  EXTI2_IRQHandler                 [WEAK]
-                EXPORT  EXTI3_IRQHandler                 [WEAK]
-                EXPORT  EXTI4_IRQHandler                 [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
-                EXPORT  ADC1_IRQHandler                  [WEAK]
-                EXPORT  EXTI9_5_IRQHandler               [WEAK]
-                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler               [WEAK]
-                EXPORT  TIM2_IRQHandler                  [WEAK]
-                EXPORT  TIM3_IRQHandler                  [WEAK]
-                EXPORT  TIM4_IRQHandler                  [WEAK]
-                EXPORT  I2C1_EV_IRQHandler               [WEAK]
-                EXPORT  I2C1_ER_IRQHandler               [WEAK]
-                EXPORT  I2C2_EV_IRQHandler               [WEAK]
-                EXPORT  I2C2_ER_IRQHandler               [WEAK]
-                EXPORT  SPI1_IRQHandler                  [WEAK]
-                EXPORT  SPI2_IRQHandler                  [WEAK]
-                EXPORT  USART1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler                [WEAK]
-                EXPORT  USART3_IRQHandler                [WEAK]
-                EXPORT  EXTI15_10_IRQHandler             [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler             [WEAK]
-                EXPORT  CEC_IRQHandler                   [WEAK]
-                EXPORT  TIM12_IRQHandler                 [WEAK]
-                EXPORT  TIM13_IRQHandler                 [WEAK]
-                EXPORT  TIM14_IRQHandler                 [WEAK]
-                EXPORT  TIM5_IRQHandler                  [WEAK]
-                EXPORT  SPI3_IRQHandler                  [WEAK]
-                EXPORT  UART4_IRQHandler                 [WEAK]
-                EXPORT  UART5_IRQHandler                 [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
-                EXPORT  TIM7_IRQHandler                  [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler         [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler         [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler         [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler       [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler         [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM15_IRQHandler
-TIM1_UP_TIM16_IRQHandler
-TIM1_TRG_COM_TIM17_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-CEC_IRQHandler
-TIM12_IRQHandler
-TIM13_IRQHandler
-TIM14_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-DMA2_Channel5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101x6.s

@@ -1,276 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f101x6.s
-;* Author             : MCD Application Team
-;* Description        : STM32F101x6 Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler            ; ADC1
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     0                          ; Reserved
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     0                          ; Reserved
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     0                          ; Reserved
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]            
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xb.s

@@ -1,286 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f101xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32F101xB Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler            ; ADC1
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xe.s

@@ -1,324 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f101xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32F101xE Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler            ; ADC1
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     FSMC_IRQHandler            ; FSMC
-                DCD     0                          ; Reserved
-                DCD     TIM5_IRQHandler            ; TIM5
-                DCD     SPI3_IRQHandler            ; SPI3
-                DCD     UART4_IRQHandler           ; UART4
-                DCD     UART5_IRQHandler           ; UART5
-                DCD     TIM6_IRQHandler            ; TIM6
-                DCD     TIM7_IRQHandler            ; TIM7
-                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0               
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  FSMC_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-FSMC_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xg.s

@@ -1,336 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f101xg.s
-;* Author             : MCD Application Team
-;* Description        : STM32F101xG Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler               ; Window Watchdog
-                DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler             ; Tamper
-                DCD     RTC_IRQHandler                ; RTC
-                DCD     FLASH_IRQHandler              ; Flash
-                DCD     RCC_IRQHandler                ; RCC
-                DCD     EXTI0_IRQHandler              ; EXTI Line 0
-                DCD     EXTI1_IRQHandler              ; EXTI Line 1
-                DCD     EXTI2_IRQHandler              ; EXTI Line 2
-                DCD     EXTI3_IRQHandler              ; EXTI Line 3
-                DCD     EXTI4_IRQHandler              ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler               ; ADC1
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
-                DCD     TIM9_IRQHandler               ; TIM9
-                DCD     TIM10_IRQHandler              ; TIM10
-                DCD     TIM11_IRQHandler              ; TIM11
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler               ; TIM2
-                DCD     TIM3_IRQHandler               ; TIM3
-                DCD     TIM4_IRQHandler               ; TIM4
-                DCD     I2C1_EV_IRQHandler            ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler            ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler            ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler            ; I2C2 Error
-                DCD     SPI1_IRQHandler               ; SPI1
-                DCD     SPI2_IRQHandler               ; SPI2
-                DCD     USART1_IRQHandler             ; USART1
-                DCD     USART2_IRQHandler             ; USART2
-                DCD     USART3_IRQHandler             ; USART3
-                DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler           ; RTC Alarm through EXTI Line
-                DCD     0                          ; Reserved
-                DCD     TIM12_IRQHandler                ; TIM12
-                DCD     TIM13_IRQHandler                ; TIM13 
-                DCD     TIM14_IRQHandler                ; TIM14
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     FSMC_IRQHandler               ; FSMC
-                DCD     0                          ; Reserved
-                DCD     TIM5_IRQHandler               ; TIM5
-                DCD     SPI3_IRQHandler               ; SPI3
-                DCD     UART4_IRQHandler              ; UART4
-                DCD     UART5_IRQHandler              ; UART5
-                DCD     TIM6_IRQHandler               ; TIM6
-                DCD     TIM7_IRQHandler               ; TIM7
-                DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0               
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler               [WEAK]
-                EXPORT  PVD_IRQHandler                [WEAK]
-                EXPORT  TAMPER_IRQHandler             [WEAK]
-                EXPORT  RTC_IRQHandler                [WEAK]
-                EXPORT  FLASH_IRQHandler              [WEAK]
-                EXPORT  RCC_IRQHandler                [WEAK]
-                EXPORT  EXTI0_IRQHandler              [WEAK]
-                EXPORT  EXTI1_IRQHandler              [WEAK]
-                EXPORT  EXTI2_IRQHandler              [WEAK]
-                EXPORT  EXTI3_IRQHandler              [WEAK]
-                EXPORT  EXTI4_IRQHandler              [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler      [WEAK]
-                EXPORT  ADC1_IRQHandler               [WEAK]
-                EXPORT  EXTI9_5_IRQHandler            [WEAK]
-                EXPORT  TIM9_IRQHandler               [WEAK]
-                EXPORT  TIM10_IRQHandler              [WEAK]
-                EXPORT  TIM11_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler               [WEAK]
-                EXPORT  TIM3_IRQHandler               [WEAK]
-                EXPORT  TIM4_IRQHandler               [WEAK]
-                EXPORT  I2C1_EV_IRQHandler            [WEAK]
-                EXPORT  I2C1_ER_IRQHandler            [WEAK]
-                EXPORT  I2C2_EV_IRQHandler            [WEAK]
-                EXPORT  I2C2_ER_IRQHandler            [WEAK]
-                EXPORT  SPI1_IRQHandler               [WEAK]
-                EXPORT  SPI2_IRQHandler               [WEAK]
-                EXPORT  USART1_IRQHandler             [WEAK]
-                EXPORT  USART2_IRQHandler             [WEAK]
-                EXPORT  USART3_IRQHandler             [WEAK]
-                EXPORT  EXTI15_10_IRQHandler          [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler          [WEAK]
-                EXPORT  TIM12_IRQHandler              [WEAK]
-                EXPORT  TIM13_IRQHandler              [WEAK]
-                EXPORT  TIM14_IRQHandler              [WEAK]
-                EXPORT  FSMC_IRQHandler               [WEAK]
-                EXPORT  TIM5_IRQHandler               [WEAK]
-                EXPORT  SPI3_IRQHandler               [WEAK]
-                EXPORT  UART4_IRQHandler              [WEAK]
-                EXPORT  UART5_IRQHandler              [WEAK]
-                EXPORT  TIM6_IRQHandler               [WEAK]
-                EXPORT  TIM7_IRQHandler               [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler    [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-EXTI9_5_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-TIM12_IRQHandler
-TIM13_IRQHandler
-TIM14_IRQHandler
-FSMC_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f102x6.s

@@ -1,283 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f102x6.s
-;* Author             : MCD Application Team
-;* Description        : STM32F102x6 Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler            ; ADC1
-                DCD     USB_HP_IRQHandler          ; USB High Priority
-                DCD     USB_LP_IRQHandler          ; USB Low  Priority
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     0                          ; Reserved
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     0                          ; Reserved
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     0                          ; Reserved
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-EXTI9_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f102xb.s

@@ -1,293 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f102xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32F102xB Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler            ; ADC1
-                DCD     USB_HP_IRQHandler          ; USB High Priority
-                DCD     USB_LP_IRQHandler          ; USB Low  Priority
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-EXTI9_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103x6.s

@@ -1,295 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f103x6.s
-;* Author             : MCD Application Team
-;* Description        : STM32F103x6 Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1_2
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     0                          ; Reserved
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     0                          ; Reserved
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     0                          ; Reserved
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xb.s

@@ -1,305 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f103xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32F103xB Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1_2
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xe.s

@@ -1,354 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f103xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32F103xE Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1 & ADC2
-                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
-                DCD     TIM8_BRK_IRQHandler        ; TIM8 Break
-                DCD     TIM8_UP_IRQHandler         ; TIM8 Update
-                DCD     TIM8_TRG_COM_IRQHandler    ; TIM8 Trigger and Commutation
-                DCD     TIM8_CC_IRQHandler         ; TIM8 Capture Compare
-                DCD     ADC3_IRQHandler            ; ADC3
-                DCD     FSMC_IRQHandler            ; FSMC
-                DCD     SDIO_IRQHandler            ; SDIO
-                DCD     TIM5_IRQHandler            ; TIM5
-                DCD     SPI3_IRQHandler            ; SPI3
-                DCD     UART4_IRQHandler           ; UART4
-                DCD     UART5_IRQHandler           ; UART5
-                DCD     TIM6_IRQHandler            ; TIM6
-                DCD     TIM7_IRQHandler            ; TIM7
-                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0               
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  USBWakeUp_IRQHandler       [WEAK]
-                EXPORT  TIM8_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM8_UP_IRQHandler         [WEAK]
-                EXPORT  TIM8_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM8_CC_IRQHandler         [WEAK]
-                EXPORT  ADC3_IRQHandler            [WEAK]
-                EXPORT  FSMC_IRQHandler            [WEAK]
-                EXPORT  SDIO_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-TIM8_BRK_IRQHandler
-TIM8_UP_IRQHandler
-TIM8_TRG_COM_IRQHandler
-TIM8_CC_IRQHandler
-ADC3_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xg.s

@@ -1,354 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f103xg.s
-;* Author             : MCD Application Team
-;* Description        : STM32F103xG Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-                                                  
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler               ; Window Watchdog
-                DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler             ; Tamper
-                DCD     RTC_IRQHandler                ; RTC
-                DCD     FLASH_IRQHandler              ; Flash
-                DCD     RCC_IRQHandler                ; RCC
-                DCD     EXTI0_IRQHandler              ; EXTI Line 0
-                DCD     EXTI1_IRQHandler              ; EXTI Line 1
-                DCD     EXTI2_IRQHandler              ; EXTI Line 2
-                DCD     EXTI3_IRQHandler              ; EXTI Line 3
-                DCD     EXTI4_IRQHandler              ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler             ; ADC1 & ADC2
-                DCD     USB_HP_CAN1_TX_IRQHandler     ; USB High Priority or CAN1 TX
-                DCD     USB_LP_CAN1_RX0_IRQHandler    ; USB Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler           ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler           ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
-                DCD     TIM1_BRK_TIM9_IRQHandler      ; TIM1 Break and TIM9
-                DCD     TIM1_UP_TIM10_IRQHandler      ; TIM1 Update and TIM10
-                DCD     TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
-                DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler               ; TIM2
-                DCD     TIM3_IRQHandler               ; TIM3
-                DCD     TIM4_IRQHandler               ; TIM4
-                DCD     I2C1_EV_IRQHandler            ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler            ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler            ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler            ; I2C2 Error
-                DCD     SPI1_IRQHandler               ; SPI1
-                DCD     SPI2_IRQHandler               ; SPI2
-                DCD     USART1_IRQHandler             ; USART1
-                DCD     USART2_IRQHandler             ; USART2
-                DCD     USART3_IRQHandler             ; USART3
-                DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler           ; RTC Alarm through EXTI Line
-                DCD     USBWakeUp_IRQHandler          ; USB Wakeup from suspend
-                DCD     TIM8_BRK_TIM12_IRQHandler     ; TIM8 Break and TIM12
-                DCD     TIM8_UP_TIM13_IRQHandler      ; TIM8 Update and TIM13
-                DCD     TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
-                DCD     TIM8_CC_IRQHandler            ; TIM8 Capture Compare
-                DCD     ADC3_IRQHandler               ; ADC3
-                DCD     FSMC_IRQHandler               ; FSMC
-                DCD     SDIO_IRQHandler               ; SDIO
-                DCD     TIM5_IRQHandler               ; TIM5
-                DCD     SPI3_IRQHandler               ; SPI3
-                DCD     UART4_IRQHandler              ; UART4
-                DCD     UART5_IRQHandler              ; UART5
-                DCD     TIM6_IRQHandler               ; TIM6
-                DCD     TIM7_IRQHandler               ; TIM7
-                DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-                
-; Reset handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0               
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-                
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler               [WEAK]
-                EXPORT  PVD_IRQHandler                [WEAK]
-                EXPORT  TAMPER_IRQHandler             [WEAK]
-                EXPORT  RTC_IRQHandler                [WEAK]
-                EXPORT  FLASH_IRQHandler              [WEAK]
-                EXPORT  RCC_IRQHandler                [WEAK]
-                EXPORT  EXTI0_IRQHandler              [WEAK]
-                EXPORT  EXTI1_IRQHandler              [WEAK]
-                EXPORT  EXTI2_IRQHandler              [WEAK]
-                EXPORT  EXTI3_IRQHandler              [WEAK]
-                EXPORT  EXTI4_IRQHandler              [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler      [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler      [WEAK]
-                EXPORT  ADC1_2_IRQHandler             [WEAK]
-                EXPORT  USB_HP_CAN1_TX_IRQHandler     [WEAK]
-                EXPORT  USB_LP_CAN1_RX0_IRQHandler    [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler           [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler           [WEAK]
-                EXPORT  EXTI9_5_IRQHandler            [WEAK]
-                EXPORT  TIM1_BRK_TIM9_IRQHandler      [WEAK]
-                EXPORT  TIM1_UP_TIM10_IRQHandler      [WEAK]
-                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
-                EXPORT  TIM1_CC_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler               [WEAK]
-                EXPORT  TIM3_IRQHandler               [WEAK]
-                EXPORT  TIM4_IRQHandler               [WEAK]
-                EXPORT  I2C1_EV_IRQHandler            [WEAK]
-                EXPORT  I2C1_ER_IRQHandler            [WEAK]
-                EXPORT  I2C2_EV_IRQHandler            [WEAK]
-                EXPORT  I2C2_ER_IRQHandler            [WEAK]
-                EXPORT  SPI1_IRQHandler               [WEAK]
-                EXPORT  SPI2_IRQHandler               [WEAK]
-                EXPORT  USART1_IRQHandler             [WEAK]
-                EXPORT  USART2_IRQHandler             [WEAK]
-                EXPORT  USART3_IRQHandler             [WEAK]
-                EXPORT  EXTI15_10_IRQHandler          [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler           [WEAK]
-                EXPORT  USBWakeUp_IRQHandler          [WEAK]
-                EXPORT  TIM8_BRK_TIM12_IRQHandler     [WEAK]
-                EXPORT  TIM8_UP_TIM13_IRQHandler      [WEAK]
-                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
-                EXPORT  TIM8_CC_IRQHandler            [WEAK]
-                EXPORT  ADC3_IRQHandler               [WEAK]
-                EXPORT  FSMC_IRQHandler               [WEAK]
-                EXPORT  SDIO_IRQHandler               [WEAK]
-                EXPORT  TIM5_IRQHandler               [WEAK]
-                EXPORT  SPI3_IRQHandler               [WEAK]
-                EXPORT  UART4_IRQHandler              [WEAK]
-                EXPORT  UART5_IRQHandler              [WEAK]
-                EXPORT  TIM6_IRQHandler               [WEAK]
-                EXPORT  TIM7_IRQHandler               [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler      [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler    [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM9_IRQHandler
-TIM1_UP_TIM10_IRQHandler
-TIM1_TRG_COM_TIM11_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-TIM8_BRK_TIM12_IRQHandler
-TIM8_UP_TIM13_IRQHandler
-TIM8_TRG_COM_TIM14_IRQHandler
-TIM8_CC_IRQHandler
-ADC3_IRQHandler
-FSMC_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f105xc.s

@@ -1,362 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f105xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32F105xC Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1 and ADC2
-                DCD     CAN1_TX_IRQHandler         ; CAN1 TX
-                DCD     CAN1_RX0_IRQHandler        ; CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C1 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC alarm through EXTI line
-                DCD     OTG_FS_WKUP_IRQHandler     ; USB OTG FS Wakeup through EXTI line
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM5_IRQHandler            ; TIM5
-                DCD     SPI3_IRQHandler            ; SPI3
-                DCD     UART4_IRQHandler           ; UART4
-                DCD     UART5_IRQHandler           ; UART5
-                DCD     TIM6_IRQHandler            ; TIM6
-                DCD     TIM7_IRQHandler            ; TIM7
-                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
-                DCD     DMA2_Channel4_IRQHandler   ; DMA2 Channel4
-                DCD     DMA2_Channel5_IRQHandler   ; DMA2 Channel5
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     CAN2_TX_IRQHandler         ; CAN2 TX
-                DCD     CAN2_RX0_IRQHandler        ; CAN2 RX0
-                DCD     CAN2_RX1_IRQHandler        ; CAN2 RX1
-                DCD     CAN2_SCE_IRQHandler        ; CAN2 SCE
-                DCD     OTG_FS_IRQHandler          ; USB OTG FS
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  CAN1_TX_IRQHandler         [WEAK]
-                EXPORT  CAN1_RX0_IRQHandler        [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  OTG_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  CAN2_TX_IRQHandler         [WEAK]
-                EXPORT  CAN2_RX0_IRQHandler        [WEAK]
-                EXPORT  CAN2_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN2_SCE_IRQHandler        [WEAK]
-                EXPORT  OTG_FS_IRQHandler          [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f107xc.s

@@ -1,366 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32f107xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32F107xC Devices vector table for MDK-ARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Configure the clock system
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler            ; Window Watchdog
-                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler          ; Tamper
-                DCD     RTC_IRQHandler             ; RTC
-                DCD     FLASH_IRQHandler           ; Flash
-                DCD     RCC_IRQHandler             ; RCC
-                DCD     EXTI0_IRQHandler           ; EXTI Line 0
-                DCD     EXTI1_IRQHandler           ; EXTI Line 1
-                DCD     EXTI2_IRQHandler           ; EXTI Line 2
-                DCD     EXTI3_IRQHandler           ; EXTI Line 3
-                DCD     EXTI4_IRQHandler           ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler          ; ADC1 and ADC2
-                DCD     CAN1_TX_IRQHandler         ; CAN1 TX
-                DCD     CAN1_RX0_IRQHandler        ; CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
-                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
-                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
-                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
-                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler            ; TIM2
-                DCD     TIM3_IRQHandler            ; TIM3
-                DCD     TIM4_IRQHandler            ; TIM4
-                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler         ; I2C1 Error
-                DCD     SPI1_IRQHandler            ; SPI1
-                DCD     SPI2_IRQHandler            ; SPI2
-                DCD     USART1_IRQHandler          ; USART1
-                DCD     USART2_IRQHandler          ; USART2
-                DCD     USART3_IRQHandler          ; USART3
-                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler        ; RTC alarm through EXTI line
-                DCD     OTG_FS_WKUP_IRQHandler     ; USB OTG FS Wakeup through EXTI line
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     TIM5_IRQHandler            ; TIM5
-                DCD     SPI3_IRQHandler            ; SPI3
-                DCD     UART4_IRQHandler           ; UART4
-                DCD     UART5_IRQHandler           ; UART5
-                DCD     TIM6_IRQHandler            ; TIM6
-                DCD     TIM7_IRQHandler            ; TIM7
-                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
-                DCD     DMA2_Channel4_IRQHandler   ; DMA2 Channel4
-                DCD     DMA2_Channel5_IRQHandler   ; DMA2 Channel5
-                DCD     ETH_IRQHandler             ; Ethernet
-                DCD     ETH_WKUP_IRQHandler        ; Ethernet Wakeup through EXTI line
-                DCD     CAN2_TX_IRQHandler         ; CAN2 TX
-                DCD     CAN2_RX0_IRQHandler        ; CAN2 RX0
-                DCD     CAN2_RX1_IRQHandler        ; CAN2 RX1
-                DCD     CAN2_SCE_IRQHandler        ; CAN2 SCE
-                DCD     OTG_FS_IRQHandler          ; USB OTG FS
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_IRQHandler          [WEAK]
-                EXPORT  RTC_IRQHandler             [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_2_IRQHandler          [WEAK]
-                EXPORT  CAN1_TX_IRQHandler         [WEAK]
-                EXPORT  CAN1_RX0_IRQHandler        [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
-                EXPORT  TIM1_UP_IRQHandler         [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
-                EXPORT  TIM1_CC_IRQHandler         [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler        [WEAK]
-                EXPORT  OTG_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  ETH_IRQHandler             [WEAK]
-                EXPORT  ETH_WKUP_IRQHandler        [WEAK]
-                EXPORT  CAN2_TX_IRQHandler         [WEAK]
-                EXPORT  CAN2_RX0_IRQHandler        [WEAK]
-                EXPORT  CAN2_RX1_IRQHandler        [WEAK]
-                EXPORT  CAN2_SCE_IRQHandler        [WEAK]
-                EXPORT  OTG_FS_IRQHandler          [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-OTG_FS_WKUP_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-ETH_IRQHandler
-ETH_WKUP_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-OTG_FS_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f100xb.s

@@ -1,407 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f100xb.s
-  * @author    MCD Application Team
-  * @brief     STM32F100xB Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_TIM15_IRQHandler
-  .word TIM1_UP_TIM16_IRQHandler
-  .word TIM1_TRG_COM_TIM17_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word CEC_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM6_DAC_IRQHandler
-  .word TIM7_IRQHandler  
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x01CC. This is for boot in RAM mode for 
-                            STM32F10xB Value Line devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM15_IRQHandler
-  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM16_IRQHandler
-  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM17_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-  
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-  
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-  
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-  
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak  CEC_IRQHandler
-  .thumb_set CEC_IRQHandler,Default_Handler
-
-  .weak  TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler  
-
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f100xe.s

@@ -1,449 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f100xe.s
-  * @author    MCD Application Team
-  * @brief     STM32F100xE Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_TIM15_IRQHandler
-  .word TIM1_UP_TIM16_IRQHandler
-  .word TIM1_TRG_COM_TIM17_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word CEC_IRQHandler
-  .word TIM12_IRQHandler
-  .word TIM13_IRQHandler
-  .word TIM14_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_DAC_IRQHandler
-  .word TIM7_IRQHandler  
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_5_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x High Density Value line devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM15_IRQHandler
-  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM16_IRQHandler
-  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM17_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak  CEC_IRQHandler
-  .thumb_set CEC_IRQHandler,Default_Handler
-
-  .weak  TIM12_IRQHandler
-  .thumb_set TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM13_IRQHandler
-  .thumb_set TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM14_IRQHandler
-  .thumb_set TIM14_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak  TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler 
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler  
-
-  .weak  DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f101x6.s

@@ -1,322 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f101x6.s
-  * @author    MCD Application Team
-  * @brief     STM32F101x6 Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word 0
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word 0
-  .word 0
-  .word SPI1_IRQHandler
-  .word 0
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word 0
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM        /* @0x108. This is for boot in RAM mode for
-                          STM32F10x Low Density devices.*/
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f101xb.s

@@ -1,338 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f101xb.s
-  * @author    MCD Application Team
-  * @brief     STM32F101xB Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for
-                            STM32F10x Medium Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f101xe.s

@@ -1,423 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f101xe.s
-  * @author    MCD Application Team
-  * @brief     STM32F101xE Value Line Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word FSMC_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM       /* @0x1E0. This is for boot in RAM mode for
-                         STM32F10x High Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f101xg.s

@@ -1,439 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f101xg.s
-  * @author    MCD Application Team
-  * @brief     STM32F101xG Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None
- * @retval None       
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  EXTI9_5_IRQHandler
-  .word  TIM9_IRQHandler
-  .word  TIM10_IRQHandler
-  .word  TIM11_IRQHandler
-  .word  0
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTC_Alarm_IRQHandler
-  .word 0
-  .word TIM12_IRQHandler
-  .word TIM13_IRQHandler
-  .word TIM14_IRQHandler
-  .word 0
-  .word 0
-  .word  FSMC_IRQHandler
-  .word 0
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_IRQHandler
-  .word  TIM7_IRQHandler
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_5_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x XL-Density devices. */
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-* 
-*******************************************************************************/
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak  TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak  TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak  TIM12_IRQHandler
-  .thumb_set TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM13_IRQHandler
-  .thumb_set TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM14_IRQHandler
-  .thumb_set TIM14_IRQHandler,Default_Handler
-
-  .weak  FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f102x6.s

@@ -1,330 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f102x6.s
-  * @author    MCD Application Team
-  * @brief     STM32F102x6 Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word 0 
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word 0
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word 0
-  .word 0
-  .word SPI1_IRQHandler
-  .word 0
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word 0
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USBWakeUp_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM        /* @0x108. This is for boot in RAM mode for
-                          STM32F10x Low Density devices.*/
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f102xb.s

@@ -1,346 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f102xb.s
-  * @author    MCD Application Team
-  * @brief     STM32F102xB Value Line Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word 0 
-  .word 0
-  .word EXTI9_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USBWakeUp_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for
-                            STM32F10x Medium Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103x6.s

@@ -1,348 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f103x6.s
-  * @author    MCD Application Team
-  * @brief     STM32F103x6 Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_2_IRQHandler
-  .word USB_HP_CAN1_TX_IRQHandler
-  .word USB_LP_CAN1_RX0_IRQHandler
-  .word CAN1_RX1_IRQHandler
-  .word CAN1_SCE_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_IRQHandler
-  .word TIM1_UP_IRQHandler
-  .word TIM1_TRG_COM_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word 0
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word 0
-  .word 0
-  .word SPI1_IRQHandler
-  .word 0
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word 0
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USBWakeUp_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM        /* @0x108. This is for boot in RAM mode for
-                          STM32F10x Low Density devices.*/
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak USB_HP_CAN1_TX_IRQHandler
-  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-  .weak USB_LP_CAN1_RX0_IRQHandler
-  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM1_BRK_IRQHandler
-  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-  .weak TIM1_UP_IRQHandler
-  .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-  .weak TIM1_TRG_COM_IRQHandler
-  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-  .weak TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xe.s

@@ -1,470 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f103xe.s
-  * @author    MCD Application Team
-  * @brief     STM32F103xE Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Configure external SRAM mounted on STM3210E-EVAL board
-  *                  to be used as data memory (optional, to be enabled by user)
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_2_IRQHandler
-  .word USB_HP_CAN1_TX_IRQHandler
-  .word USB_LP_CAN1_RX0_IRQHandler
-  .word CAN1_RX1_IRQHandler
-  .word CAN1_SCE_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_IRQHandler
-  .word TIM1_UP_IRQHandler
-  .word TIM1_TRG_COM_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USBWakeUp_IRQHandler
-  .word TIM8_BRK_IRQHandler
-  .word TIM8_UP_IRQHandler
-  .word TIM8_TRG_COM_IRQHandler
-  .word TIM8_CC_IRQHandler
-  .word ADC3_IRQHandler
-  .word FSMC_IRQHandler
-  .word SDIO_IRQHandler
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_5_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM       /* @0x1E0. This is for boot in RAM mode for
-                         STM32F10x High Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak USB_HP_CAN1_TX_IRQHandler
-  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-  .weak USB_LP_CAN1_RX0_IRQHandler
-  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM1_BRK_IRQHandler
-  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-  .weak TIM1_UP_IRQHandler
-  .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-  .weak TIM1_TRG_COM_IRQHandler
-  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-  .weak TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-  .weak TIM8_BRK_IRQHandler
-  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
-
-  .weak TIM8_UP_IRQHandler
-  .thumb_set TIM8_UP_IRQHandler,Default_Handler
-
-  .weak TIM8_TRG_COM_IRQHandler
-  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
-
-  .weak TIM8_CC_IRQHandler
-  .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-  .weak ADC3_IRQHandler
-  .thumb_set ADC3_IRQHandler,Default_Handler
-
-  .weak FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xg.s

@@ -1,466 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f103xb.s
-  * @author    MCD Application Team
-  * @brief     STM32F103xB Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM,        0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None
- * @retval None       
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word  WWDG_IRQHandler
-  .word  PVD_IRQHandler
-  .word  TAMPER_IRQHandler
-  .word  RTC_IRQHandler
-  .word  FLASH_IRQHandler
-  .word  RCC_IRQHandler
-  .word  EXTI0_IRQHandler
-  .word  EXTI1_IRQHandler
-  .word  EXTI2_IRQHandler
-  .word  EXTI3_IRQHandler
-  .word  EXTI4_IRQHandler
-  .word  DMA1_Channel1_IRQHandler
-  .word  DMA1_Channel2_IRQHandler
-  .word  DMA1_Channel3_IRQHandler
-  .word  DMA1_Channel4_IRQHandler
-  .word  DMA1_Channel5_IRQHandler
-  .word  DMA1_Channel6_IRQHandler
-  .word  DMA1_Channel7_IRQHandler
-  .word  ADC1_2_IRQHandler
-  .word  USB_HP_CAN1_TX_IRQHandler
-  .word  USB_LP_CAN1_RX0_IRQHandler
-  .word  CAN1_RX1_IRQHandler
-  .word  CAN1_SCE_IRQHandler
-  .word  EXTI9_5_IRQHandler
-  .word  TIM1_BRK_TIM9_IRQHandler
-  .word  TIM1_UP_TIM10_IRQHandler
-  .word  TIM1_TRG_COM_TIM11_IRQHandler
-  .word  TIM1_CC_IRQHandler
-  .word  TIM2_IRQHandler
-  .word  TIM3_IRQHandler
-  .word  TIM4_IRQHandler
-  .word  I2C1_EV_IRQHandler
-  .word  I2C1_ER_IRQHandler
-  .word  I2C2_EV_IRQHandler
-  .word  I2C2_ER_IRQHandler
-  .word  SPI1_IRQHandler
-  .word  SPI2_IRQHandler
-  .word  USART1_IRQHandler
-  .word  USART2_IRQHandler
-  .word  USART3_IRQHandler
-  .word  EXTI15_10_IRQHandler
-  .word  RTC_Alarm_IRQHandler
-  .word  USBWakeUp_IRQHandler
-  .word  TIM8_BRK_TIM12_IRQHandler
-  .word  TIM8_UP_TIM13_IRQHandler
-  .word  TIM8_TRG_COM_TIM14_IRQHandler
-  .word  TIM8_CC_IRQHandler
-  .word  ADC3_IRQHandler
-  .word  FSMC_IRQHandler
-  .word  SDIO_IRQHandler
-  .word  TIM5_IRQHandler
-  .word  SPI3_IRQHandler
-  .word  UART4_IRQHandler
-  .word  UART5_IRQHandler
-  .word  TIM6_IRQHandler
-  .word  TIM7_IRQHandler
-  .word  DMA2_Channel1_IRQHandler
-  .word  DMA2_Channel2_IRQHandler
-  .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_5_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x XL-Density devices. */
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-* 
-*******************************************************************************/
-    
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-  
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-  
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-  
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak  USB_HP_CAN1_TX_IRQHandler
-  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
-  .weak  USB_LP_CAN1_RX0_IRQHandler
-  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_TIM9_IRQHandler
-  .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_TIM10_IRQHandler
-  .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_TIM11_IRQHandler
-  .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak  USBWakeUp_IRQHandler
-  .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-  .weak  TIM8_BRK_TIM12_IRQHandler
-  .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
-  .weak  TIM8_UP_TIM13_IRQHandler
-  .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
-  .weak  TIM8_TRG_COM_TIM14_IRQHandler
-  .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
-  .weak  TIM8_CC_IRQHandler
-  .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-  .weak  ADC3_IRQHandler
-  .thumb_set ADC3_IRQHandler,Default_Handler
-
-  .weak  FSMC_IRQHandler
-  .thumb_set FSMC_IRQHandler,Default_Handler
-
-  .weak  SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_5_IRQHandler
-  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f105xc.s

@@ -1,463 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f105xc.s
-  * @author    MCD Application Team
-  * @brief     STM32F105xC Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None
- * @retval None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_2_IRQHandler
-  .word CAN1_TX_IRQHandler
-  .word CAN1_RX0_IRQHandler
-   .word CAN1_RX1_IRQHandler
-  .word CAN1_SCE_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_IRQHandler
-  .word TIM1_UP_IRQHandler
-  .word TIM1_TRG_COM_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word OTG_FS_WKUP_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word 0
-  .word CAN2_TX_IRQHandler
-  .word CAN2_RX0_IRQHandler
-  .word CAN2_RX1_IRQHandler
-  .word CAN2_SCE_IRQHandler
-  .word OTG_FS_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM     /* @0x1E0. This is for boot in RAM mode for
-                         STM32F10x Connectivity line Devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak CAN1_TX_IRQHandler
-  .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
-  .weak CAN1_RX0_IRQHandler
-  .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM1_BRK_IRQHandler
-  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-  .weak TIM1_UP_IRQHandler
-  .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-  .weak TIM1_TRG_COM_IRQHandler
-  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-  .weak TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak OTG_FS_WKUP_IRQHandler
-  .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak CAN2_TX_IRQHandler
-  .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
-  .weak CAN2_RX0_IRQHandler
-  .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
-  .weak CAN2_RX1_IRQHandler
-  .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
-  .weak CAN2_SCE_IRQHandler
-  .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
-  .weak OTG_FS_IRQHandler
-  .thumb_set OTG_FS_IRQHandler ,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f107xc.s

@@ -1,472 +0,0 @@
-/**
-  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
-  * @file      startup_stm32f107xc.s
-  * @author    MCD Application Team
-  * @brief     STM32F107xC Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system   
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017-2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF1E0F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Call the clock system initialization function.*/
-    bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_2_IRQHandler
-  .word CAN1_TX_IRQHandler
-  .word CAN1_RX0_IRQHandler
-  .word CAN1_RX1_IRQHandler
-  .word CAN1_SCE_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word TIM1_BRK_IRQHandler
-  .word TIM1_UP_IRQHandler
-  .word TIM1_TRG_COM_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word OTG_FS_WKUP_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word ETH_IRQHandler
-  .word ETH_WKUP_IRQHandler
-  .word CAN2_TX_IRQHandler
-  .word CAN2_RX0_IRQHandler
-  .word CAN2_RX1_IRQHandler
-  .word CAN2_SCE_IRQHandler
-  .word OTG_FS_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM     /* @0x1E0. This is for boot in RAM mode for
-                         STM32F10x Connectivity line Devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-  .weak  NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak  HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak  MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak  BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak  UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak  SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak  DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak  PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak  SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak  WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak  PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak  TAMPER_IRQHandler
-  .thumb_set TAMPER_IRQHandler,Default_Handler
-
-  .weak  RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-
-  .weak  FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak  RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak  EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak  EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak  EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak  EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak  EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak  DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak  ADC1_2_IRQHandler
-  .thumb_set ADC1_2_IRQHandler,Default_Handler
-
-  .weak  CAN1_TX_IRQHandler
-  .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX0_IRQHandler
-  .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN1_RX1_IRQHandler
-  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN1_SCE_IRQHandler
-  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-  .weak  EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak  TIM1_BRK_IRQHandler
-  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-  .weak  TIM1_UP_IRQHandler
-  .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-  .weak  TIM1_TRG_COM_IRQHandler
-  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-  .weak  TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-  .weak  TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak  TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak  TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak  I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak  I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak  I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak  I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak  SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak  SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak  USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak  USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak  USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak  EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak  RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak  OTG_FS_WKUP_IRQHandler
-  .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak  TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-
-  .weak  SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak  UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak  UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-
-  .weak  TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak  TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak  ETH_IRQHandler
-  .thumb_set ETH_IRQHandler,Default_Handler
-
-  .weak  ETH_WKUP_IRQHandler
-  .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
-  .weak  CAN2_TX_IRQHandler
-  .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
-  .weak  CAN2_RX0_IRQHandler
-  .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN2_RX1_IRQHandler
-  .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN2_SCE_IRQHandler
-  .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
-  .weak  OTG_FS_IRQHandler
-  .thumb_set OTG_FS_IRQHandler ,Default_Handler
-

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f100xb_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20001FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f100xb_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20001FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f100xe_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f100xe_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101x6_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x08007FFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x200017FF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101x6_sram.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__     = 0x200017FF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/linker/stm32f101xb_flash.icf

@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x400;
-define symbol __ICFEDIT_size_heap__     = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };